Add PLL7 (USB2 PLL) for 1060 MCUs

PLL7 is required to use the secondary USB controller. PLL3 is only used for the primary USB controller.

I briefly read through the imxrt1060 specification to ensure that it was intended to be clocked identically. I can't imagine much else needs verification, as this addition seems relatively simple.

src/chip/imxrt10xx/ccm/analog/pll7.rs

@@ -0,0 +1,43 @@
+//! The USB2 PLL.
+//!
+//! This PLL is associated with USB2, the secondary USB interface.
+
+/// PLL7 frequency (Hz).
+///
+/// The reference manual notes that PLL7 should always run at 480MHz,
+/// so this constant assumes that PLL7's DIV_SELECT field isn't
+/// changed at runtime.
+pub const FREQUENCY: u32 = 480_000_000;
+
+/// The smallest PLL7_PFD divider.
+pub const MIN_FRAC: u8 = 12;
+/// The largest PLL7_PFD divider.
+pub const MAX_FRAC: u8 = 35;
+
+use crate::ral;
+
+/// Restart the USB2 PLL.
+pub fn restart(ccm_analog: &mut ral::ccm_analog::CCM_ANALOG) {
+    loop {
+        if ral::read_reg!(ral::ccm_analog, ccm_analog, PLL_USB2, ENABLE == 0) {
+            ral::write_reg!(ral::ccm_analog, ccm_analog, PLL_USB2_SET, ENABLE: 1);
+            continue;
+        }
+        if ral::read_reg!(ral::ccm_analog, ccm_analog, PLL_USB2, POWER == 0) {
+            ral::write_reg!(ral::ccm_analog, ccm_analog, PLL_USB2_SET, POWER: 1);
+            continue;
+        }
+        if ral::read_reg!(ral::ccm_analog, ccm_analog, PLL_USB2, LOCK == 0) {
+            continue;
+        }
+        if ral::read_reg!(ral::ccm_analog, ccm_analog, PLL_USB2, BYPASS == 1) {
+            ral::write_reg!(ral::ccm_analog, ccm_analog, PLL_USB2_CLR, BYPASS: 1);
+            continue;
+        }
+        if ral::read_reg!(ral::ccm_analog, ccm_analog, PLL_USB2, EN_USB_CLKS == 0) {
+            ral::write_reg!(ral::ccm_analog, ccm_analog, PLL_USB2_SET, EN_USB_CLKS: 1);
+            continue;
+        }
+        break;
+    }
+}

src/chip/imxrt10xx/imxrt1060.rs

@@ -23,6 +23,7 @@ pub(crate) mod ccm {
 
     pub(crate) mod analog {
         pub mod pll1;
+        pub mod pll7;
     }
 
     /// Re-exported by the common clock_gate module.