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[Conversion] lowering XeGPU.ops to VC-Intrinsics #669

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Nov 10, 2023
Merged

[Conversion] lowering XeGPU.ops to VC-Intrinsics #669

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4 changes: 4 additions & 0 deletions include/imex/Conversion/Passes.td
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Original file line number Diff line number Diff line change
Expand Up @@ -250,6 +250,10 @@ memref, arith and math.
}];
let constructor = "imex::createConvertGPUXToSPIRVPass()";
let dependentDialects = ["::mlir::spirv::SPIRVDialect"];
let options = [
Option<"enableSimtIntrinsic", "enable-simt-intrinsic","bool", "false",
"Enable XeGPU.simt Ops lowered to intel genISA simt Intrinsics">
];
}

//===----------------------------------------------------------------------===//
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46 changes: 18 additions & 28 deletions include/imex/Dialect/XeGPU/IR/XeGPUOps.td
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Expand Up @@ -575,38 +575,28 @@ def XeGPU_InvokeSIMDOp : XeGPU_Op<"invoke_SIMD", []> {

}

def XeGPU_AtomicRMWOp
: XeGPU_Op<"atomic_rmw", []> {
let summary = "performa ready-modify-write operation that is free from data races.";

let arguments = (ins
XeGPU_AtomicRMWKindAttr:$kind,
XeGPU_Vector2DType:$value,
XeGPU_TensorDesc:$tensorDesc,
XeGPU_MaskType:$mask,
DefaultValuedAttr<XeGPU_ModeAttr, "imex::xegpu::Mode::SIMT">: $mode
);

let assemblyFormat = [{
$kind $value `,` $tensorDesc `,` $mask (`{` `mode` `=` $mode^ `}`)?
attr-dict
`:` `(` qualified(type($value)) `,` qualified(type($tensorDesc)) `,` qualified(type($mask)) `)`
}];
}
def XeGPU_AtomicRMWOp: XeGPU_Op<"atomic_rmw", []> {
let summary = "perform ready-modify-write operation that is free from data races.";
let arguments = (ins
XeGPU_AtomicRMWKindAttr:$kind,
XeGPU_TensorDesc:$tensorDesc,
XeGPU_MaskType:$mask,
Optional<XeGPU_ValueType>:$value,
DefaultValuedAttr<XeGPU_ModeAttr, "imex::xegpu::Mode::SIMT">: $mode
);
let results = (outs XeGPU_ValueType:$result);
let assemblyFormat = [{
$kind $tensorDesc `,` $mask (`,` $value^)? (`{` `mode` `=` $mode^ `}`)? attr-dict `:` qualified(type(operands)) `->` type($result)
}];
}


def XeGPU_AllocNbarrierOp
: XeGPU_Op<"alloc_nbarrier", []> {
def XeGPU_AllocNbarrierOp: XeGPU_Op<"alloc_nbarrier", []> {
let summary = "allocate a specific number of named barriers.";
let arguments = (ins I32Attr: $nbarrierCount);
let assemblyFormat = "$nbarrierCount attr-dict";
}

let arguments = (ins
I8: $nbarrier_count
);

let assemblyFormat = [{
$nbarrier_count attr-dict `:` qualified(type($nbarrier_count))
}];
}

def XeGPU_CreateNbarrierOp
: XeGPU_Op<"create_nbarrier", []> {
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5 changes: 4 additions & 1 deletion lib/Conversion/GPUToSPIRV/GPUToSPIRVPass.cpp
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Expand Up @@ -158,7 +158,8 @@ void GPUXToSPIRVPass::runOnOperation() {
target->addIllegalDialect<imex::xegpu::XeGPUDialect>();
typeConverter.addConversion(
[&](xegpu::TensorDescType type) -> ::mlir::Type {
return ::mlir::IntegerType::get(context, 64);
auto i64Type = ::mlir::IntegerType::get(context, 64);
return ::mlir::VectorType::get(2, i64Type);
});
typeConverter.addConversion([&](::mlir::VectorType type) -> ::mlir::Type {
unsigned rank = type.getRank();
Expand All @@ -175,6 +176,8 @@ void GPUXToSPIRVPass::runOnOperation() {
for (unsigned i = 0; i < rank; i++) {
sum *= type.getShape()[i];
}
if (llvm::isa<mlir::IndexType>(elemType))
elemType = ::mlir::IntegerType::get(context, 64);
return ::mlir::VectorType::get(sum, elemType);
}
});
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