GitHub - jkirschner/evolverilog: Using evolutionary algorithms in Python to generate Verilog hardware implementations

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Using evolutionary algorithms in Python to generate Verilog hardware implementations

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Name		Name	Last commit message	Last commit date
Latest commit History 166 Commits
TestCode		TestCode
gen1		gen1
.gitignore		.gitignore
4bAdder.v		4bAdder.v
BooleanLogic.py		BooleanLogic.py
FamousWinner.v		FamousWinner.v
Organism.py		Organism.py
OrganismManager.py		OrganismManager.py
README		README
Terminator.py		Terminator.py
Tree.py		Tree.py
TreeOrganism.py		TreeOrganism.py
TreeWithVisualizer.py		TreeWithVisualizer.py
exampleScootBot.v		exampleScootBot.v
exampleScootBot_old.v		exampleScootBot_old.v
fourBoolCorrect.v		fourBoolCorrect.v
organismToVerilogTest.v		organismToVerilogTest.v
runScootBot.py		runScootBot.py
scootBot.v		scootBot.v
scootBotTest.v		scootBotTest.v
selector.py		selector.py
simpleAnd_test.v		simpleAnd_test.v
simulateScootBot.v		simulateScootBot.v
test.png		test.png
testOrgs.py		testOrgs.py
text.png		text.png

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EvolVerilog

An evolving verilog-coder

Written by

Jared Kirschner
Shane Moon
Matt Belland
Paul Booth

Requires:
Icarus verilog (iverilog and vvp)
Python
matplotlib python module