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greth_library
greth_library PublicA debugging transport based on greth 10/100Mbit and riscv_vhdl
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ibex
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Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
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sysver2ver
sysver2ver PublicForked from jrrk/sysver2ver
Converting System Verilog to plain Verilog using .xml dump from Verilator
Verilog 2
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