Simplified MIPS in Verilog

Implementation of a simplified version of the MIPS Pipeline in Verilog hardware description language.

The pipeline implemented in this repository has 5 stages.

Running

You will need Icarus Verilog to run our code. It is a Verilog simulation and synthesis tool.

Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
DOC		DOC
.gitattributes		.gitattributes
.gitignore		.gitignore
Alu.v		Alu.v
Comparator.v		Comparator.v
Control.v		Control.v
Decode.v		Decode.v
Execute.v		Execute.v
FPGA.v		FPGA.v
Fetch.v		Fetch.v
MemController.v		MemController.v
Memory.v		Memory.v
Mips.v		Mips.v
README.md		README.md
Registers.v		Registers.v
Shifter.v		Shifter.v
Writeback.v		Writeback.v