This is a VHDL code for 4bit multiplier using 4bit full adder circuit structurally modelled. you can find
in four_bit_multiplier.vhd and test bench of it in four_bit_multiplier_tb.vhd you can find
in forbit_fulladder.vhd and test bench of it in forbit_fulladder_tb.vhd you can find
in fulladder.vhd and test bench of it in fulladder_tb.vhd