Skip to content

Commit

Permalink
remove sdram options
Browse files Browse the repository at this point in the history
  • Loading branch information
@pepijndevos
pepijndevos committed Aug 22, 2024
1 parent d0b0aaa commit 835afdc
Show file tree
Hide file tree
Showing 3 changed files with 25 additions and 27 deletions.
4 changes: 1 addition & 3 deletions litex_boards/targets/sipeed_tang_nano_20k.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,6 @@ def __init__(self, sys_clk_freq=48e6,
with_led_chaser = True,
with_rgb_led = False,
with_buttons = True,
with_sdram = False,
toolchain = "gowin",
**kwargs):

Expand All @@ -72,7 +71,7 @@ def __init__(self, sys_clk_freq=48e6,
# TODO: XTX SPI Flash

# SDR SDRAM --------------------------------------------------------------------------------
if with_sdram and not self.integrated_main_ram_size:
if not self.integrated_main_ram_size:
class SDRAMPads:
def __init__(self):
self.clk = platform.request("O_sdram_clk")
Expand Down Expand Up @@ -127,7 +126,6 @@ def main():
parser = LiteXArgumentParser(platform=sipeed_tang_nano_20k.Platform, description="LiteX SoC on Tang Nano 20K.")
parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.")
parser.add_target_argument("--sys-clk-freq", default=48e6, type=float, help="System clock frequency.")
parser.add_target_argument("--with-sdram", action="store_true", help="Enable optional SDRAM module.")
sdopts = parser.target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
Expand Down
5 changes: 1 addition & 4 deletions litex_boards/targets/sipeed_tang_nano_9k.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -62,7 +62,6 @@ class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=27e6, bios_flash_offset=0x0,
with_led_chaser = True,
with_video_terminal = False,
with_sdram = False,
toolchain = "gowin",
**kwargs):
platform = sipeed_tang_nano_9k.Platform(toolchain=toolchain)
Expand All @@ -89,7 +88,7 @@ def __init__(self, sys_clk_freq=27e6, bios_flash_offset=0x0,
self.cpu.set_reset_address(self.bus.regions["rom"].origin)

# HyperRAM ---------------------------------------------------------------------------------
if with_sdram and not self.integrated_main_ram_size:
if not self.integrated_main_ram_size:
# TODO: Use second 32Mbit PSRAM chip.
dq = platform.request("IO_psram_dq")
rwds = platform.request("IO_psram_rwds")
Expand Down Expand Up @@ -139,7 +138,6 @@ def main():
parser.add_target_argument("--bios-flash-offset", default="0x0", help="BIOS offset in SPI Flash.")
parser.add_target_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
parser.add_target_argument("--with-sdram", action="store_true", help="Enable optional SDRAM module.")
parser.add_target_argument("--prog-kit", default="openfpgaloader", help="Programmer select from Gowin/openFPGALoader.")
args = parser.parse_args()

Expand All @@ -148,7 +146,6 @@ def main():
sys_clk_freq = args.sys_clk_freq,
bios_flash_offset = int(args.bios_flash_offset, 0),
with_video_terminal = args.with_video_terminal,
with_sdram=args.with_sdram,
**parser.soc_argdict
)

Expand Down
43 changes: 23 additions & 20 deletions litex_boards/targets/sipeed_tang_primer_20k.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@
# CRG ----------------------------------------------------------------------------------------------

class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq, with_video_pll=False):
def __init__(self, platform, sys_clk_freq, with_video_pll=False, with_clkdiv=False):
self.rst = Signal()
self.cd_sys = ClockDomain()
self.cd_por = ClockDomain()
Expand All @@ -58,20 +58,23 @@ def __init__(self, platform, sys_clk_freq, with_video_pll=False):
self.pll = pll = GW2APLL(devicename=platform.devicename, device=platform.device)
self.comb += pll.reset.eq(~por_done)
pll.register_clkin(clk27, 27e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
self.specials += [
Instance("DHCEN",
i_CLKIN = self.cd_sys2x_i.clk,
i_CE = self.stop,
o_CLKOUT = self.cd_sys2x.clk),
Instance("CLKDIV",
p_DIV_MODE = "2",
i_CALIB = 0,
i_HCLKIN = self.cd_sys2x.clk,
i_RESETN = ~self.reset,
o_CLKOUT = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.rst | self.reset),
]
if with_clkdiv:
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
self.specials += [
Instance("DHCEN",
i_CLKIN = self.cd_sys2x_i.clk,
i_CE = self.stop,
o_CLKOUT = self.cd_sys2x.clk),
Instance("CLKDIV",
p_DIV_MODE = "2",
i_CALIB = 0,
i_HCLKIN = self.cd_sys2x.clk,
i_RESETN = ~self.reset,
o_CLKOUT = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.rst | self.reset),
]
else:
pll.create_clkout(self.cd_sys, sys_clk_freq)

# Init clock domain
self.comb += self.cd_init.clk.eq(clk27)
Expand Down Expand Up @@ -101,11 +104,11 @@ def __init__(self, sys_clk_freq=48e6,
with_rgb_led = False,
with_buttons = True,
with_video_terminal = False,
with_clkdiv = False,
with_ethernet = False,
with_etherbone = False,
eth_ip = "192.168.1.50",
eth_dynamic_ip = False,
with_sdram = False,
dock = "standard",
toolchain = "gowin",
**kwargs):
Expand All @@ -118,13 +121,13 @@ def __init__(self, sys_clk_freq=48e6,
with_led_chaser = False # No leds on core board nor on dock lite.

# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal)
self.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal, with_clkdiv=with_clkdiv)

# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Primer 20K", **kwargs)

# DDR3 SDRAM -------------------------------------------------------------------------------
if with_sdram and not self.integrated_main_ram_size:
if not self.integrated_main_ram_size:
self.ddrphy = GW2DDRPHY(
pads = platform.request("ddram"),
sys_clk_freq = sys_clk_freq
Expand Down Expand Up @@ -200,9 +203,9 @@ def main():
sdopts = parser.target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_target_argument("--with-sdram", action="store_true", help="Enable optional SDRAM module.")
parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
parser.add_target_argument("--with-clkdiv", action="store_true", help="Use clock divider for system clock.")
ethopts = parser.target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone.")
Expand All @@ -215,7 +218,7 @@ def main():
sys_clk_freq = args.sys_clk_freq,
with_spi_flash = args.with_spi_flash,
with_video_terminal = args.with_video_terminal,
with_sdram = args.with_sdram,
with_clkdiv = args.with_clkdiv,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
Expand Down

0 comments on commit 835afdc

Please sign in to comment.