Skip to content

Commit

Permalink
improve terasic_de2_115 target support
Browse files Browse the repository at this point in the history
  • Loading branch information
Sergey Anufrienko committed Oct 23, 2023
1 parent 0d560bc commit ce95158
Show file tree
Hide file tree
Showing 2 changed files with 152 additions and 3 deletions.
75 changes: 75 additions & 0 deletions litex_boards/platforms/terasic_de2_115.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,27 @@
_io = [
# Clk
("clk50", 0, Pins("Y2"), IOStandard("3.3-V LVTTL")),
("clk25", 0, Pins("A14"), IOStandard("3.3-V LVTTL")),

# Red LEDs
("user_led", 0, Pins("G19"), IOStandard("2.5 V")),
("user_led", 1, Pins("F19"), IOStandard("2.5 V")),
("user_led", 2, Pins("E19"), IOStandard("2.5 V")),
("user_led", 3, Pins("F21"), IOStandard("2.5 V")),
("user_led", 4, Pins("F18"), IOStandard("2.5 V")),
("user_led", 5, Pins("E18"), IOStandard("2.5 V")),
("user_led", 6, Pins("J19"), IOStandard("2.5 V")),
("user_led", 7, Pins("H19"), IOStandard("2.5 V")),
("user_led", 8, Pins("J17"), IOStandard("2.5 V")),
("user_led", 9, Pins("G17"), IOStandard("2.5 V")),
("user_led", 10, Pins("J15"), IOStandard("2.5 V")),
("user_led", 11, Pins("H16"), IOStandard("2.5 V")),
("user_led", 12, Pins("J16"), IOStandard("2.5 V")),
("user_led", 13, Pins("H17"), IOStandard("2.5 V")),
("user_led", 14, Pins("F15"), IOStandard("2.5 V")),
("user_led", 15, Pins("G15"), IOStandard("2.5 V")),
("user_led", 16, Pins("G16"), IOStandard("2.5 V")),
("user_led", 17, Pins("H15"), IOStandard("2.5 V")),

# Serial
("serial", 0,
Expand All @@ -38,6 +59,59 @@
Subsignal("dm", Pins("U2 W4")),
IOStandard("3.3-V LVTTL")
),

# SD Card
("sdcard", 0,
Subsignal("data", Pins("AE14 AF13 AB14 AC14")),
Subsignal("cmd", Pins("AD14")),
Subsignal("clk", Pins("AE13")),
Misc("FAST_OUTPUT_REGISTER ON"),
IOStandard("3.3-V LVTTL"),
),

# MII Ethernet (88E1111)
("eth_clocks", 0,
Subsignal("tx", Pins("B17")),
Subsignal("rx", Pins("A15")),
IOStandard("2.5 V")
),
("eth", 0,
Subsignal("rst_n", Pins("C19")),
Subsignal("int_n", Pins("A21")),
Subsignal("mdio", Pins("B21")),
Subsignal("mdc", Pins("C20")),
Subsignal("rx_dv", Pins("C17")),
Subsignal("rx_er", Pins("D18")),
Subsignal("rx_data", Pins("C16 D16 D17 C15")),
Subsignal("tx_en", Pins("A18")),
Subsignal("tx_er", Pins("B18")),
Subsignal("tx_data", Pins("C18 D19 A19 B19")),
Subsignal("col", Pins("E15")),
Subsignal("crs", Pins("D15")),
IOStandard("2.5 V")
),

# MII Ethernet (88E1111)
("eth_clocks", 1,
Subsignal("tx", Pins("C22")),
Subsignal("rx", Pins("B15")),
IOStandard("2.5 V")
),
("eth", 1,
Subsignal("rst_n", Pins("D22")),
Subsignal("int_n", Pins("D24")),
Subsignal("mdio", Pins("D25")),
Subsignal("mdc", Pins("D23")),
Subsignal("rx_dv", Pins("A22")),
Subsignal("rx_er", Pins("C24")),
Subsignal("rx_data", Pins("B23 C21 A23 D21")),
Subsignal("tx_en", Pins("B25")),
Subsignal("tx_er", Pins("A25")),
Subsignal("tx_data", Pins("C25 A26 B26 C26")),
Subsignal("col", Pins("B22")),
Subsignal("crs", Pins("D20")),
IOStandard("2.5 V")
),
]

# Platform -----------------------------------------------------------------------------------------
Expand All @@ -55,3 +129,4 @@ def create_programmer(self):
def do_finalize(self, fragment):
AlteraPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
80 changes: 77 additions & 3 deletions litex_boards/targets/terasic_de2_115.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,12 +16,15 @@
from litex_boards.platforms import terasic_de2_115

from litex.soc.cores.clock import CycloneIVPLL
from litex.soc.cores.led import LedChaser
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *

from litedram.modules import IS42S16320
from litedram.phy import GENSDRPHY

from liteeth.phy.mii import LiteEthPHYMII

# CRG ----------------------------------------------------------------------------------------------

class _CRG(LiteXModule):
Expand All @@ -48,7 +51,18 @@ def __init__(self, platform, sys_clk_freq):
# BaseSoC ------------------------------------------------------------------------------------------

class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=50e6, **kwargs):
def __init__(
self,
sys_clk_freq=50e6,
with_ethernet=False,
with_etherbone=False,
with_sdcard=False,
with_led_chaser=True,
ethernet_phy=0,
etherbone_ip="192.168.1.50",
etherbone_phy=1,
**kwargs,
):
platform = terasic_de2_115.Platform()

# CRG --------------------------------------------------------------------------------------
Expand All @@ -66,18 +80,78 @@ def __init__(self, sys_clk_freq=50e6, **kwargs):
l2_cache_size = kwargs.get("l2_size", 8192)
)

# Add debug interface if the CPU has one ---------------------------------------------------
if hasattr(self.cpu, "debug_bus"):
self.register_mem(
name="vexriscv_debug",
address=0xF00F0000,
interface=self.cpu.debug_bus,
size=0x100,
)

# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(
pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq
)
self.leds.add_pwm()

# SD Card ----------------------------------------------------------------------------------
if with_sdcard:
self.add_sdcard()

# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=platform.request("eth_clocks", ethernet_phy),
pads=platform.request("eth", ethernet_phy),
)
self.add_ethernet(
phy=self.ethphy,
phy_cd="ethphy_eth" if with_etherbone else "eth",
dynamic_ip=True,
)
if with_etherbone:
# Ethernet PHY
self.submodules.ethbphy = LiteEthPHYMII(
clock_pads=platform.request("eth_clocks", etherbone_phy),
pads=platform.request("eth", etherbone_phy),
)
self.add_etherbone(
phy=self.ethbphy,
phy_cd="ethbphy_eth" if with_ethernet else "eth",
ip_address=etherbone_ip,
)

# Build --------------------------------------------------------------------------------------------

def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=terasic_de2_115.Platform, description="LiteX SoC on DE2-115.")

parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
parser.add_target_argument("--with-led-chaser", action="store_true", help="Enable LED chaser.")
parser.add_target_argument("--with-sdcard", action="store_true", help="Enable SD card support.")
parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
parser.add_target_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_target_argument("--etherbone-ip", default="192.168.48.100", help="Etherbone IP address.")
parser.add_target_argument("--etherbone-phy", default=1, type=int, help="Etherbone PHY (0 or 1).")
parser.add_target_argument("--ethernet-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
args = parser.parse_args()

soc = BaseSoC(
sys_clk_freq = args.sys_clk_freq,
**parser.soc_argdict
sys_clk_freq=args.sys_clk_freq,
with_sdcard=args.with_sdcard,
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
with_led_chaser=args.with_led_chaser,
etherbone_ip=args.etherbone_ip,
etherbone_phy=args.etherbone_phy,
ethernet_phy=args.ethernet_phy,
**parser.soc_argdict,
)

builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**parser.toolchain_argdict)
Expand Down

0 comments on commit ce95158

Please sign in to comment.