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Merge pull request #513 from josuah/master
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lattice_ecp5_evn: add_jtagbone flag
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enjoy-digital authored Aug 1, 2023
2 parents 2d3b81a + 538399c commit f780b5f
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Showing 2 changed files with 15 additions and 7 deletions.
15 changes: 8 additions & 7 deletions litex_boards/prog/openocd_evn_ecp5.cfg
Original file line number Diff line number Diff line change
@@ -1,9 +1,10 @@
interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 0
ftdi_layout_init 0xfff8 0xfffb
adapter driver ftdi
adapter speed 25000
transport select jtag
ftdi vid_pid 0x0403 0x6010
ftdi channel 0
ftdi layout_init 0x00e8 0x60eb
reset_config none

adapter_khz 5000

jtag newtap ecp5 tap -irlen 8 -expected-id 0x81113043
set _CHIPNAME ecp5
jtag newtap $_CHIPNAME tap -irlen 8 -expected-id 0x81113043
7 changes: 7 additions & 0 deletions litex_boards/targets/lattice_ecp5_evn.py
Original file line number Diff line number Diff line change
Expand Up @@ -46,6 +46,7 @@ def __init__(self, platform, sys_clk_freq, x5_clk_freq):
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=50e6, toolchain="trellis", x5_clk_freq=None,
with_led_chaser = True,
with_jtagbone = True,
**kwargs):
platform = lattice_ecp5_evn.Platform(toolchain=toolchain)

Expand All @@ -55,6 +56,10 @@ def __init__(self, sys_clk_freq=50e6, toolchain="trellis", x5_clk_freq=None,
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ECP5 Evaluation Board", **kwargs)

# JtagBone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()

# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(
Expand All @@ -68,12 +73,14 @@ def main():
parser = LiteXArgumentParser(platform=lattice_ecp5_evn.Platform, description="LiteX SoC on ECP5 Evaluation Board.")
parser.add_target_argument("--sys-clk-freq", default=60e6, type=float, help="System clock frequency.")
parser.add_target_argument("--x5-clk-freq", type=int, help="Use X5 oscillator as system clock at the specified frequency.")
parser.add_target_argument("--with-jtagbone", action="store_true", help="Add JTAGBone.")
args = parser.parse_args()

soc = BaseSoC(
toolchain = args.toolchain,
sys_clk_freq = args.sys_clk_freq,
x5_clk_freq = args.x5_clk_freq,
with_jtagbone = args.with_jtagbone,
**parser.soc_argdict)
builder = Builder(soc, **parser.builder_argdict)
if args.build:
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