platforms/crosslink_nx_evn: add SPI flash support

[josuah]

This appears to work to me:

(litex-3.11) lap1$1 litex_term /dev/ttyUSB1

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2023 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Aug 11 2023 16:21:15
 BIOS CRC passed (b12549e4)

 LiteX git sha1: 577674bf

--=============== SoC ==================--
CPU:            VexRiscv @ 75MHz
BUS:            WISHBONE 32-bit @ 4GiB
CSR:            32-bit data
ROM:            128.0KiB
SRAM:           128.0KiB
FLASH:          16.0MiB

--========== Initialization ============--

Initializing MX25L12833F SPI Flash @0x01000000...
Enabling Quad mode...
Switching to QPI mode...
SPI Flash clk configured to 0 MHz
Memspeed at 0x1000000 (Sequential, 4.0KiB)...
   Read speed: 7.2MiB/s
Memspeed at 0x1000000 (Random, 4.0KiB)...
   Read speed: 2.3MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> mem_list
Available memory regions:
ROM       0x00000000 0x20000
SRAM      0x10000000 0x20000
SPIFLASH  0x01000000 0x1000000
CSR       0xf0000000 0x10000

litex> mem_read 0x01000000 100
Memory dump:
0x01000000  49 20 62 65 6c 69 65 76 65 20 74 68 69 73 20 69  I believe this i
0x01000010  73 20 6f 6e 20 74 68 65 20 66 6c 61 73 68 2c 20  s on the flash,
0x01000020  61 6e 64 20 74 68 61 74 20 77 65 20 63 61 6e 20  and that we can
0x01000030  72 65 61 64 20 69 74 20 62 61 63 6b 20 77 69 74  read it back wit
0x01000040  68 6f 75 74 20 70 72 6f 62 6c 65 6d 2e 20 44 6f  hout problem. Do
0x01000050  6e 27 74 20 79 6f 75 3f 0a ff ff ff ff ff ff ff  n't you?........
0x01000060  ff ff ff ff                                      ....

litex>

I took inspiration on the other boards, is this done the right way?

[enjoy-digital]

Thanks @josuah, this looks good and has been merged.