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[AArch64][GlobalISel] Add a number of ptr shufflevector tests. NFC
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@davemgreen
davemgreen committed Nov 13, 2024
1 parent d7263d6 commit 42da815
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13 changes: 12 additions & 1 deletion llvm/test/CodeGen/AArch64/arm64-ext.ll
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@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI

; CHECK-GI: warning: Instruction selection used fallback path for test_v2p0

define <8 x i8> @test_vextd(<8 x i8> %tmp1, <8 x i8> %tmp2) {
; CHECK-LABEL: test_vextd:
Expand Down Expand Up @@ -131,3 +133,12 @@ define <2 x i64> @test_v2s64(<2 x i64> %a, <2 x i64> %b) {
%s = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 0>
ret <2 x i64> %s
}

define <2 x ptr> @test_v2p0(<2 x ptr> %a, <2 x ptr> %b) {
; CHECK-LABEL: test_v2p0:
; CHECK: // %bb.0:
; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #8
; CHECK-NEXT: ret
%s = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 3, i32 0>
ret <2 x ptr> %s
}
71 changes: 55 additions & 16 deletions llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
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@@ -1,51 +1,90 @@
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-GI

; Extract of an upper half of a vector is an "ext.16b v0, v0, v0, #8" insn.

define <8 x i8> @v8i8(<16 x i8> %a) nounwind {
; CHECK: v8i8
; CHECK: ext.16b v0, v0, v0, #8
; CHECK: ret
; CHECK-LABEL: v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ext.16b v0, v0, v0, #8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%ret = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <8 x i8> %ret
}

define <4 x i16> @v4i16(<8 x i16> %a) nounwind {
; CHECK-LABEL: v4i16:
; CHECK: ext.16b v0, v0, v0, #8
; CHECK: ret
; CHECK: // %bb.0:
; CHECK-NEXT: ext.16b v0, v0, v0, #8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%ret = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
ret <4 x i16> %ret
}

define <2 x i32> @v2i32(<4 x i32> %a) nounwind {
; CHECK-LABEL: v2i32:
; CHECK: ext.16b v0, v0, v0, #8
; CHECK: ret
; CHECK: // %bb.0:
; CHECK-NEXT: ext.16b v0, v0, v0, #8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%ret = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3>
ret <2 x i32> %ret
}

define <1 x i64> @v1i64(<2 x i64> %a) nounwind {
; CHECK-LABEL: v1i64:
; CHECK: ext.16b v0, v0, v0, #8
; CHECK: ret
; CHECK-SD-LABEL: v1i64:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v1i64:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov d0, v0[1]
; CHECK-GI-NEXT: ret
%ret = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> <i32 1>
ret <1 x i64> %ret
}

define <1 x ptr> @v1p0(<2 x ptr> %a) nounwind {
; CHECK-SD-LABEL: v1p0:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v1p0:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov d0, v0[1]
; CHECK-GI-NEXT: ret
%ret = shufflevector <2 x ptr> %a, <2 x ptr> %a, <1 x i32> <i32 1>
ret <1 x ptr> %ret
}

define <2 x float> @v2f32(<4 x float> %a) nounwind {
; CHECK-LABEL: v2f32:
; CHECK: ext.16b v0, v0, v0, #8
; CHECK: ret
; CHECK: // %bb.0:
; CHECK-NEXT: ext.16b v0, v0, v0, #8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%ret = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> <i32 2, i32 3>
ret <2 x float> %ret
}

define <1 x double> @v1f64(<2 x double> %a) nounwind {
; CHECK-LABEL: v1f64:
; CHECK: ext.16b v0, v0, v0, #8
; CHECK: ret
; CHECK-SD-LABEL: v1f64:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v1f64:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov d0, v0[1]
; CHECK-GI-NEXT: ret
%ret = shufflevector <2 x double> %a, <2 x double> %a, <1 x i32> <i32 1>
ret <1 x double> %ret
}
69 changes: 68 additions & 1 deletion llvm/test/CodeGen/AArch64/neon-perm.ll
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Original file line number Diff line number Diff line change
@@ -1,6 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI

; CHECK-GI: warning: Instruction selection used fallback path for test_vuzp1q_p0
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vuzp2q_p0
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vzip1q_p0
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vzip2q_p0
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vtrn1q_p0
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vtrn2q_p0

%struct.int8x8x2_t = type { [2 x <8 x i8>] }
%struct.int16x4x2_t = type { [2 x <4 x i16>] }
Expand Down Expand Up @@ -161,6 +168,16 @@ entry:
ret <2 x i64> %shuffle.i
}

define <2 x ptr> @test_vuzp1q_p0(<2 x ptr> %a, <2 x ptr> %b) {
; CHECK-LABEL: test_vuzp1q_p0:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 0, i32 2>
ret <2 x ptr> %shuffle.i
}

define <2 x float> @test_vuzp1_f32(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: test_vuzp1_f32:
; CHECK: // %bb.0: // %entry
Expand Down Expand Up @@ -371,6 +388,16 @@ entry:
ret <2 x i64> %shuffle.i
}

define <2 x ptr> @test_vuzp2q_p0(<2 x ptr> %a, <2 x ptr> %b) {
; CHECK-LABEL: test_vuzp2q_p0:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: zip2 v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 1, i32 3>
ret <2 x ptr> %shuffle.i
}

define <2 x float> @test_vuzp2_f32(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: test_vuzp2_f32:
; CHECK: // %bb.0: // %entry
Expand Down Expand Up @@ -581,6 +608,16 @@ entry:
ret <2 x i64> %shuffle.i
}

define <2 x ptr> @test_vzip1q_p0(<2 x ptr> %a, <2 x ptr> %b) {
; CHECK-LABEL: test_vzip1q_p0:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 0, i32 2>
ret <2 x ptr> %shuffle.i
}

define <2 x float> @test_vzip1_f32(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: test_vzip1_f32:
; CHECK: // %bb.0: // %entry
Expand Down Expand Up @@ -791,6 +828,16 @@ entry:
ret <2 x i64> %shuffle.i
}

define <2 x ptr> @test_vzip2q_p0(<2 x ptr> %a, <2 x ptr> %b) {
; CHECK-LABEL: test_vzip2q_p0:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: zip2 v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 1, i32 3>
ret <2 x ptr> %shuffle.i
}

define <2 x float> @test_vzip2_f32(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: test_vzip2_f32:
; CHECK: // %bb.0: // %entry
Expand Down Expand Up @@ -1001,6 +1048,16 @@ entry:
ret <2 x i64> %shuffle.i
}

define <2 x ptr> @test_vtrn1q_p0(<2 x ptr> %a, <2 x ptr> %b) {
; CHECK-LABEL: test_vtrn1q_p0:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 0, i32 2>
ret <2 x ptr> %shuffle.i
}

define <2 x float> @test_vtrn1_f32(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: test_vtrn1_f32:
; CHECK: // %bb.0: // %entry
Expand Down Expand Up @@ -1211,6 +1268,16 @@ entry:
ret <2 x i64> %shuffle.i
}

define <2 x ptr> @test_vtrn2q_p0(<2 x ptr> %a, <2 x ptr> %b) {
; CHECK-LABEL: test_vtrn2q_p0:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: zip2 v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret
entry:
%shuffle.i = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 1, i32 3>
ret <2 x ptr> %shuffle.i
}

define <2 x float> @test_vtrn2_f32(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: test_vtrn2_f32:
; CHECK: // %bb.0: // %entry
Expand Down
18 changes: 14 additions & 4 deletions llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,16 @@ entry:
ret <2 x i64> %V128
}

define <2 x ptr> @v2p0(<2 x ptr> %a) {
; CHECK-LABEL: v2p0:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: ret
entry:
%V128 = shufflevector <2 x ptr> %a, <2 x ptr> undef, <2 x i32> <i32 1, i32 0>
ret <2 x ptr> %V128
}

define <4 x i32> @v4i32(<4 x i32> %a) {
; CHECK-LABEL: v4i32:
; CHECK: // %bb.0: // %entry
Expand Down Expand Up @@ -46,9 +56,9 @@ entry:
define <8 x i16> @v8i16_2(<4 x i16> %a, <4 x i16> %b) {
; CHECK-LABEL: v8i16_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, .LCPI4_0
; CHECK-NEXT: adrp x8, .LCPI5_0
; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI4_0]
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI5_0]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-NEXT: ret
Expand Down Expand Up @@ -81,9 +91,9 @@ entry:
define <16 x i8> @v16i8_2(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: v16i8_2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, .LCPI7_0
; CHECK-NEXT: adrp x8, .LCPI8_0
; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI7_0]
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI8_0]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-NEXT: ret
Expand Down
10 changes: 10 additions & 0 deletions llvm/test/CodeGen/AArch64/neon-vector-splat.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -85,3 +85,13 @@ define <2 x i64> @shuffle7(ptr %P) {
%sv2i64 = shufflevector <2 x i64> %lv2i64, <2 x i64> undef, <2 x i32> zeroinitializer
ret <2 x i64> %sv2i64
}

define <2 x ptr> @shuffle8(ptr %P) {
; CHECK-LABEL: shuffle8:
; CHECK: // %bb.0:
; CHECK-NEXT: ld1r { v0.2d }, [x0]
; CHECK-NEXT: ret
%lv2ptr = load <2 x ptr>, ptr %P
%sv2ptr = shufflevector <2 x ptr> %lv2ptr, <2 x ptr> undef, <2 x i32> zeroinitializer
ret <2 x ptr> %sv2ptr
}
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