Add behavior to handle unmapped muxes without constant inputs better

docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst

@@ -59,6 +59,10 @@ build_architecture_bitstream
 
     Show verbose log
 
+  .. option:: --fix_unmapped_mux_selection
+
+    Try to connect unmapped mux outputs to unmapped inputs. Only effective if there is no constant input to muxes.
+
 build_fabric_bitstream
 ~~~~~~~~~~~~~~~~~~~~~~
 

openfpga/src/base/openfpga_bitstream_command_template.h

@@ -81,6 +81,9 @@ ShellCommandId add_build_arch_bitstream_command_template(
   /* Add an option '--verbose' */
   shell_cmd.add_option("verbose", false, "Enable verbose output");
 
+  /* Add an option '--fix_unmapped_mux_selection' */
+  shell_cmd.add_option("fix_unmapped_mux_selection", false, "Try to connect unmapped mux outputs to unmapped inputs");
+
   /* Add command 'build_architecture_bitstream' to the Shell */
   ShellCommandId shell_cmd_id = shell.add_command(
     shell_cmd, "Build fabric-independent bitstream database", hidden);

openfpga/src/base/openfpga_bitstream_template.h

@@ -39,13 +39,18 @@ int fpga_bitstream_template(T& openfpga_ctx, const Command& cmd,
   CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
   CommandOptionId opt_write_file = cmd.option("write_file");
   CommandOptionId opt_read_file = cmd.option("read_file");
+  CommandOptionId opt_fix_unmapped = cmd.option("fix_unmapped_mux_selection");
 
   if (true == cmd_context.option_enable(cmd, opt_read_file)) {
     openfpga_ctx.mutable_bitstream_manager() = read_xml_architecture_bitstream(
       cmd_context.option_value(cmd, opt_read_file).c_str());
   } else {
     openfpga_ctx.mutable_bitstream_manager() = build_device_bitstream(
-      g_vpr_ctx, openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose));
+      g_vpr_ctx,
+      openfpga_ctx,
+      cmd_context.option_enable(cmd, opt_verbose),
+      cmd_context.option_enable(cmd, opt_fix_unmapped)
+    );
   }
 
   overwrite_bitstream(openfpga_ctx.mutable_bitstream_manager(),

openfpga/src/fpga_bitstream/build_device_bitstream.cpp

@@ -149,7 +149,8 @@ static size_t rec_estimate_device_bitstream_num_bits(
  *******************************************************************/
 BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
                                         const OpenfpgaContext& openfpga_ctx,
-                                        const bool& verbose) {
+                                        bool verbose,
+                                        bool fix_unmapped_mux_selection) {
   std::string timer_message =
     std::string("\nBuild fabric-independent bitstream for implementation '") +
     vpr_ctx.atom().nlist.netlist_name() + std::string("'\n");
@@ -218,7 +219,9 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
     openfpga_ctx.vpr_device_annotation(),
     openfpga_ctx.vpr_clustering_annotation(),
     openfpga_ctx.vpr_placement_annotation(),
-    openfpga_ctx.vpr_bitstream_annotation(), verbose);
+    openfpga_ctx.vpr_bitstream_annotation(),
+    verbose,
+    fix_unmapped_mux_selection);
   VTR_LOGV(verbose, "Done\n");
 
   /* Create bitstream from routing architectures */
@@ -229,7 +232,9 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
     openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(), vpr_ctx.atom(),
     openfpga_ctx.vpr_device_annotation(), openfpga_ctx.vpr_routing_annotation(),
     vpr_ctx.device().rr_graph, openfpga_ctx.device_rr_gsb(),
-    openfpga_ctx.flow_manager().compress_routing(), verbose);
+    openfpga_ctx.flow_manager().compress_routing(),
+    verbose,
+    fix_unmapped_mux_selection);
 
   VTR_LOGV(verbose, "Done\n");
 

openfpga/src/fpga_bitstream/build_device_bitstream.h

@@ -18,7 +18,8 @@ namespace openfpga {
 
 BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
                                         const OpenfpgaContext& openfpga_ctx,
-                                        const bool& verbose);
+                                        bool verbose,
+                                        bool fix_unmapped_mux_selection);
 
 } /* end namespace openfpga */
 

openfpga/src/fpga_bitstream/build_grid_bitstream.cpp

@@ -185,7 +185,9 @@ static void build_physical_block_pin_interc_bitstream(
   const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprBitstreamAnnotation& bitstream_annotation,
   const PhysicalPb& physical_pb, t_pb_graph_pin* des_pb_graph_pin,
-  t_mode* physical_mode, const bool& verbose) {
+  t_mode* physical_mode,
+  bool verbose,
+  bool fix_unmapped_mux_selection) {
   /* Identify the number of fan-in (Consider interconnection edges of only
    * selected mode) */
   t_interconnect* cur_interc =
@@ -230,11 +232,34 @@ static void build_physical_block_pin_interc_bitstream(
       const PhysicalPbId& des_pb_id =
         physical_pb.find_pb(des_pb_graph_pin->parent_node);
       size_t mux_input_pin_id = 0;
-      if (true != physical_pb.valid_pb_id(des_pb_id)) {
+      if (true != physical_pb.valid_pb_id(des_pb_id)) { /* Unmapped pb */
         mux_input_pin_id = DEFAULT_PATH_ID;
-      } else if (AtomNetId::INVALID() == physical_pb.pb_graph_pin_atom_net(
+      } else if (AtomNetId::INVALID() == physical_pb.pb_graph_pin_atom_net( /* Unmapped output */
                                            des_pb_id, des_pb_graph_pin)) {
-        mux_input_pin_id = DEFAULT_PATH_ID;
+        if(false == circuit_lib.mux_add_const_input(mux_model) && fix_unmapped_mux_selection){
+          /* No constant input and fix flag is set, select the last unmapped input */
+          auto pin_inputs = pb_graph_pin_inputs(des_pb_graph_pin, cur_interc);
+          int pin_id;
+          for (pin_id = pin_inputs.size() - 1; pin_id >= 0; --pin_id) {
+            auto src_pb_graph_pin = pin_inputs[pin_id];
+            const PhysicalPbId& src_pb_id = physical_pb.find_pb(src_pb_graph_pin->parent_node);
+            if (!physical_pb.valid_pb_id(src_pb_id)) {
+              mux_input_pin_id = pin_id;
+              break;
+            }
+          }
+          /* Couldn't find an unmapped input, use default path ID */
+          if (pin_id == -1){
+            VTR_LOG_WARN("At PhysicalPbId=%d: output is unmapped but all inputs are mapped\n", des_pb_id);
+            mux_input_pin_id = DEFAULT_PATH_ID;
+          }
+          /* or the last input was already unmapped, use default path ID */
+          if(mux_input_pin_id == pin_inputs.size() - 1) {
+            mux_input_pin_id = DEFAULT_PATH_ID;
+          }
+        } else {
+          mux_input_pin_id = DEFAULT_PATH_ID; /* We have constant input, use the default path ID */
+        }
       } else {
         output_net =
           physical_pb.pb_graph_pin_atom_net(des_pb_id, des_pb_graph_pin);
@@ -385,7 +410,8 @@ static void build_physical_block_interc_port_bitstream(
   const VprBitstreamAnnotation& bitstream_annotation,
   t_pb_graph_node* physical_pb_graph_node, const PhysicalPb& physical_pb,
   const e_circuit_pb_port_type& pb_port_type, t_mode* physical_mode,
-  const bool& verbose) {
+  bool verbose,
+  bool fix_unmapped_mux_selection) {
   switch (pb_port_type) {
     case CIRCUIT_PB_PORT_INPUT:
       for (int iport = 0; iport < physical_pb_graph_node->num_input_ports;
@@ -398,7 +424,7 @@ static void build_physical_block_interc_port_bitstream(
             circuit_lib, mux_lib, atom_ctx, device_annotation,
             bitstream_annotation, physical_pb,
             &(physical_pb_graph_node->input_pins[iport][ipin]), physical_mode,
-            verbose);
+            verbose, fix_unmapped_mux_selection);
         }
       }
       break;
@@ -413,7 +439,7 @@ static void build_physical_block_interc_port_bitstream(
             circuit_lib, mux_lib, atom_ctx, device_annotation,
             bitstream_annotation, physical_pb,
             &(physical_pb_graph_node->output_pins[iport][ipin]), physical_mode,
-            verbose);
+            verbose, fix_unmapped_mux_selection);
         }
       }
       break;
@@ -428,7 +454,7 @@ static void build_physical_block_interc_port_bitstream(
             circuit_lib, mux_lib, atom_ctx, device_annotation,
             bitstream_annotation, physical_pb,
             &(physical_pb_graph_node->clock_pins[iport][ipin]), physical_mode,
-            verbose);
+            verbose, fix_unmapped_mux_selection);
         }
       }
       break;
@@ -451,7 +477,9 @@ static void build_physical_block_interc_bitstream(
   const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprBitstreamAnnotation& bitstream_annotation,
   t_pb_graph_node* physical_pb_graph_node, const PhysicalPb& physical_pb,
-  t_mode* physical_mode, const bool& verbose) {
+  t_mode* physical_mode,
+  bool verbose,
+  bool fix_unmapped_mux_selection) {
   /* Check if the pb_graph node is valid or not */
   if (nullptr == physical_pb_graph_node) {
     VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid physical_pb_graph_node.\n");
@@ -472,7 +500,8 @@ static void build_physical_block_interc_bitstream(
     bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block,
     module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx,
     device_annotation, bitstream_annotation, physical_pb_graph_node,
-    physical_pb, CIRCUIT_PB_PORT_OUTPUT, physical_mode, verbose);
+    physical_pb, CIRCUIT_PB_PORT_OUTPUT, physical_mode, verbose,
+    fix_unmapped_mux_selection);
 
   /* We check input_pins of child_pb_graph_node and its the input_edges
    * Iterate over the interconnections between inputs of physical_pb_graph_node
@@ -496,14 +525,14 @@ static void build_physical_block_interc_bitstream(
         parent_configurable_block, module_manager, module_name_map, circuit_lib,
         mux_lib, atom_ctx, device_annotation, bitstream_annotation,
         child_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_INPUT, physical_mode,
-        verbose);
+        verbose, fix_unmapped_mux_selection);
       /* For clock pins, we should do the same work */
       build_physical_block_interc_port_bitstream(
         bitstream_manager, grouped_mem_inst_scoreboard,
         parent_configurable_block, module_manager, module_name_map, circuit_lib,
         mux_lib, atom_ctx, device_annotation, bitstream_annotation,
         child_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_CLOCK, physical_mode,
-        verbose);
+        verbose, fix_unmapped_mux_selection);
     }
   }
 }
@@ -712,7 +741,7 @@ static void rec_build_physical_block_bitstream(
   const VprBitstreamAnnotation& bitstream_annotation, const e_side& border_side,
   const PhysicalPb& physical_pb, const PhysicalPbId& pb_id,
   t_pb_graph_node* physical_pb_graph_node, const size_t& pb_graph_node_index,
-  const bool& verbose) {
+  bool verbose, bool fix_unmapped_mux_selection) {
   /* Get the physical pb_type that is linked to the pb_graph node */
   t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type;
 
@@ -773,7 +802,7 @@ static void rec_build_physical_block_bitstream(
           child_pb,
           &(physical_pb_graph_node
               ->child_pb_graph_nodes[physical_mode->index][ipb][jpb]),
-          jpb, verbose);
+          jpb, verbose, fix_unmapped_mux_selection);
       }
     }
   }
@@ -817,7 +846,7 @@ static void rec_build_physical_block_bitstream(
     bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block,
     module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx,
     device_annotation, bitstream_annotation, physical_pb_graph_node,
-    physical_pb, physical_mode, verbose);
+    physical_pb, physical_mode, verbose, fix_unmapped_mux_selection);
 }
 
 /********************************************************************
@@ -836,7 +865,9 @@ static void build_physical_block_bitstream(
   const VprPlacementAnnotation& place_annotation,
   const VprBitstreamAnnotation& bitstream_annotation, const DeviceGrid& grids,
   const size_t& layer, const vtr::Point<size_t>& grid_coord,
-  const e_side& border_side, const bool& verbose) {
+  const e_side& border_side,
+  bool verbose,
+  bool fix_unmapped_mux_selection) {
   /* Create a block for the grid in bitstream manager */
   t_physical_tile_type_ptr grid_type = grids.get_physical_type(
     t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer));
@@ -931,7 +962,7 @@ static void build_physical_block_bitstream(
           grid_configurable_block, module_manager, module_name_map, circuit_lib,
           mux_lib, atom_ctx, device_annotation, bitstream_annotation,
           border_side, PhysicalPb(), PhysicalPbId::INVALID(),
-          lb_type->pb_graph_head, z, verbose);
+          lb_type->pb_graph_head, z, verbose, fix_unmapped_mux_selection);
       } else {
         const PhysicalPb& phy_pb = cluster_annotation.physical_pb(
           place_annotation.grid_blocks(grid_coord)[z]);
@@ -946,7 +977,7 @@ static void build_physical_block_bitstream(
           bitstream_manager, grouped_mem_inst_scoreboard,
           grid_configurable_block, module_manager, module_name_map, circuit_lib,
           mux_lib, atom_ctx, device_annotation, bitstream_annotation,
-          border_side, phy_pb, top_pb_id, pb_graph_head, z, verbose);
+          border_side, phy_pb, top_pb_id, pb_graph_head, z, verbose, fix_unmapped_mux_selection);
       }
     }
   }
@@ -966,7 +997,9 @@ void build_grid_bitstream(
   const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprClusteringAnnotation& cluster_annotation,
   const VprPlacementAnnotation& place_annotation,
-  const VprBitstreamAnnotation& bitstream_annotation, const bool& verbose) {
+  const VprBitstreamAnnotation& bitstream_annotation,
+  bool verbose,
+  bool fix_unmapped_mux_selection) {
   VTR_LOGV(verbose, "Generating bitstream for core grids...");
 
   /* Generate bitstream for the core logic block one by one */
@@ -1007,7 +1040,8 @@ void build_grid_bitstream(
         bitstream_manager, parent_block, module_manager, module_name_map,
         fabric_tile, curr_tile, circuit_lib, mux_lib, atom_ctx,
         device_annotation, cluster_annotation, place_annotation,
-        bitstream_annotation, grids, layer, grid_coord, NUM_2D_SIDES, verbose);
+        bitstream_annotation, grids, layer, grid_coord, NUM_2D_SIDES,
+        verbose, fix_unmapped_mux_selection);
     }
   }
   VTR_LOGV(verbose, "Done\n");
@@ -1055,7 +1089,8 @@ void build_grid_bitstream(
         bitstream_manager, parent_block, module_manager, module_name_map,
         fabric_tile, curr_tile, circuit_lib, mux_lib, atom_ctx,
         device_annotation, cluster_annotation, place_annotation,
-        bitstream_annotation, grids, layer, io_coordinate, io_side, verbose);
+        bitstream_annotation, grids, layer, io_coordinate, io_side,
+        verbose, fix_unmapped_mux_selection);
     }
   }
   VTR_LOGV(verbose, "Done\n");

openfpga/src/fpga_bitstream/build_grid_bitstream.h

@@ -34,7 +34,9 @@ void build_grid_bitstream(
   const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation,
   const VprClusteringAnnotation& cluster_annotation,
   const VprPlacementAnnotation& place_annotation,
-  const VprBitstreamAnnotation& bitstream_annotation, const bool& verbose);
+  const VprBitstreamAnnotation& bitstream_annotation,
+  bool verbose,
+  bool fix_unmapped_mux_selection);
 
 } /* end namespace openfpga */