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[test] relax route W to bypass VPR bugs
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@tangxifan
tangxifan committed Nov 14, 2024
1 parent d121538 commit e863333
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2 changes: 2 additions & 0 deletions ...ic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf
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Expand Up @@ -53,6 +53,8 @@ bench1_openfpga_vpr_route_chan_width=44

bench2_top = rst_and_clk_on_lut
bench2_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_and_clk.xml
# Triggered a bug in VPR, when route_chan_width=40, it failed
bench2_openfpga_vpr_route_chan_width=44

[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
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