Output preferred sides of pins for each block in an FPGA fabric w.r.t. architecture definition

[tangxifan]

Is your feature request related to a problem? Please describe.
During physical design phase, physical location pins of major blocks in an FPGA fabric may be constrained.
For example, for a CLB tile, the input pins I[0:25] should be placed on the top side of the block.
Though the pin location is already defined in VPR architecture description file

        <pinlocations pattern="custom">
          <loc side="left">clb.clk clb.reset</loc>
          <loc side="top">clb.I[13:0] clb.O[11:0] clb.lclk clb.lreset clb.cin</loc>
          <loc side="right">clb.I[25:14] clb.O[23:12]</loc>
          <loc side="bottom">clb.cout</loc>
        </pinlocations>

However, when building the fabric, both pin name and tile name are changed to OpenFPGA's convention, in order to adapt to Verilog syntax. In practice, engineers may need the corresponding pin in a different context than CLB. For instance, engineers may want to constrain pin locations at tile-level rather than CLB-level.
For example, the CLB tile is named as tile or any customized name through the rename_modules command, and the pin name I in the context is actually grid_clb_I_0_

Describe the solution you'd like
A new command should be added to OpenFPGA shell:

write_fabric_pin_physical_location --module <string> --verbose --file <string> --no_time_stamp --show_invalid_sides

where,

• user can specify the module name whose pin location should be outputted, through option --module. If the module does not exist, an error will return. If not specified, all the modules will be outputted (use regex "*"). Regular expression is supported.
• user can specify the file name where results will be written to, through option --file. Currently, only XML file format will be supported. Here is an example of the file
• user can enable option --show_invalid_sides to display sides for each pin, even these pin does not have a specific valid side. This is mainly used for debugging.

<pin_location>
  <module name="tile">
    <loc pin="grid_clb_cin" side="top"/>
    <loc pin="grid_clb_O_1_" side="right"/>
    <loc pin="grid_clb_I_0_" side="left"/>
    <loc pin="grid_clb_cout" side="bottom"/>
  </module>
</pin_locaiton>

• time stamp in resulting file can be removed through --no_time_stamp
• verbose output can be enabled thorugh --verbose