Support different routing channel width in X and and Y axis

[tangxifan]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue:
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

Currently, OpenFPGA has the following limitations:

• VPR supports different routing channel width in X and Y axis. For example, X-direction routing channel width is 30 while Y-direction routing channel width is 20. This is very useful to alleviate routing congestion when some programmable blocks have a large number of pins to access routing on some sides.
• VPR also support different wire distribution in X and Y axis routing channels. For example, X-direction routing channel width is 30 but contains 80% L1 and 20% L4, while Y-direction routing channel width is 20 but contains 80% L1 and 20% L8. This is very useful in optimizing routing architecture when some programmable block pins require different wire lengths.

However, these features are yet tested in OpenFPGA!!!

What does this pull request change?

This PR improves in the following aspects:

• Update openfpga to support the two features above.
• Added two testcases to validate the new features.

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.