[lib] update vtr to latest

libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp

@@ -6,7 +6,7 @@
 # Input file: /home/xifan/github/OpenFPGA/libs/libopenfpgacapnproto/gen/unique_blocks.xsd
 # md5sum of input file: 1db9d740309076fa51f61413bae1e072
 
-@0xb1073886de13324f;
+@0xdda3f3f93e497b0c;
 using Cxx = import "/capnp/c++.capnp";
 $Cxx.namespace("ucap");
 

openfpga/src/annotation/annotate_rr_graph.cpp

@@ -686,8 +686,9 @@ static void annotate_direct_circuit_models(
   VprDeviceAnnotation& vpr_device_annotation, const bool& verbose_output) {
   size_t count = 0;
 
-  for (int idirect = 0; idirect < vpr_device_ctx.arch->num_directs; ++idirect) {
-    std::string direct_name = vpr_device_ctx.arch->Directs[idirect].name;
+  for (size_t idirect = 0; idirect < vpr_device_ctx.arch->directs.size();
+       ++idirect) {
+    std::string direct_name = vpr_device_ctx.arch->directs[idirect].name;
     /* The name-to-circuit mapping is stored in either cb_switch-to-circuit or
      * sb_switch-to-circuit, Try to find one and update the device annotation
      */

openfpga/src/annotation/openfpga_annotate_routing.cpp

@@ -83,15 +83,16 @@ vtr::vector<RRNodeId, ClusterNetId> annotate_rr_node_global_net(
         VTR_LOG_ERROR(
           "When annotating global net '%s', invalid rr node pin type for '%s' "
           "pin '%d'\n",
-          cluster_nlist.net_name(net_id).c_str(), phy_tile->name, node_pin_num);
+          cluster_nlist.net_name(net_id).c_str(), phy_tile->name.c_str(),
+          node_pin_num);
         exit(1);
       }
       std::vector<RRNodeId> curr_rr_nodes =
         rr_graph.node_lookup().find_nodes_at_all_sides(
           layer, blk_loc.loc.x, blk_loc.loc.y, rr_pin_type, node_pin_num);
       for (RRNodeId curr_rr_node : curr_rr_nodes) {
         VTR_LOGV(verbose, "Annotate global net '%s' on '%s' pin '%d'\n",
-                 cluster_nlist.net_name(net_id).c_str(), phy_tile->name,
+                 cluster_nlist.net_name(net_id).c_str(), phy_tile->name.c_str(),
                  node_pin_num);
         rr_node_nets[curr_rr_node] = net_id;
         counter++;

openfpga/src/base/openfpga_pb_pin_fixup.cpp

@@ -185,7 +185,7 @@ static int update_cluster_pin_with_post_routing_results(
         VTR_LOG_ERROR(
           "For tile '%s', found pin '%s' on %lu sides. Expect only 1. "
           "Following info is for debugging:\n",
-          physical_tile->name,
+          physical_tile->name.c_str(),
           get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)
             ->to_string()
             .c_str(),
@@ -204,7 +204,7 @@ static int update_cluster_pin_with_post_routing_results(
         VTR_LOG_ERROR(
           "For tile '%s', found pin '%s' on the boundary side '%s', which is "
           "not physically possible.\n",
-          physical_tile->name,
+          physical_tile->name.c_str(),
           get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)
             ->to_string()
             .c_str(),
@@ -215,7 +215,7 @@ static int update_cluster_pin_with_post_routing_results(
         VTR_LOG_ERROR(
           "For tile '%s', found pin '%s' on %lu sides. Expect only 1. "
           "Following info is for debugging:\n",
-          physical_tile->name,
+          physical_tile->name.c_str(),
           get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)
             ->to_string()
             .c_str(),
@@ -233,7 +233,7 @@ static int update_cluster_pin_with_post_routing_results(
         VTR_LOG_ERROR(
           "For boundary tile '%s', expect pin '%s' only on the side '%s' but "
           "found on the following sides:\n",
-          physical_tile->name,
+          physical_tile->name.c_str(),
           get_pb_graph_node_pin_from_block_pin(blk_id, physical_pin)
             ->to_string()
             .c_str(),

openfpga/src/fabric/build_fabric_io_location_map.cpp

@@ -76,7 +76,7 @@ static IoLocationMap build_fabric_fine_grained_io_location_map(
     if (size_t(phy_tile_type->capacity) !=
         module_manager.io_children(child).size()) {
       VTR_LOG("%s[%ld][%ld] capacity: %d while io_child number is %d",
-              phy_tile_type->name, coord.x(), coord.y(),
+              phy_tile_type->name.c_str(), coord.x(), coord.y(),
               phy_tile_type->capacity,
               module_manager.io_children(child).size());
     }
@@ -211,7 +211,7 @@ static IoLocationMap build_fabric_tiled_io_location_map(
       if (size_t(phy_tile_type->capacity) !=
           module_manager.io_children(tile_child).size()) {
         VTR_LOG("%s[%ld][%ld] capacity: %d while io_child number is %d",
-                phy_tile_type->name, coord.x(), coord.y(),
+                phy_tile_type->name.c_str(), coord.x(), coord.y(),
                 phy_tile_type->capacity,
                 module_manager.io_children(tile_child).size());
       }

openfpga/src/fpga_spice/spice_grid.cpp

@@ -290,10 +290,11 @@ static void print_spice_physical_tile_netlist(
   if (true == is_io_type(phy_block_type)) {
     SideManager side_manager(border_side);
     VTR_LOG("Writing SPICE Netlist '%s' for physical tile '%s' at %s side ...",
-            spice_fname.c_str(), phy_block_type->name, side_manager.c_str());
+            spice_fname.c_str(), phy_block_type->name.c_str(),
+            side_manager.c_str());
   } else {
     VTR_LOG("Writing SPICE Netlist '%s' for physical_tile '%s'...",
-            spice_fname.c_str(), phy_block_type->name);
+            spice_fname.c_str(), phy_block_type->name.c_str());
   }
 
   /* Create the file stream */

openfpga/src/fpga_verilog/verilog_grid.cpp

@@ -315,10 +315,11 @@ static void print_verilog_physical_tile_netlist(
     SideManager side_manager(border_side);
     VTR_LOG(
       "Writing Verilog Netlist '%s' for physical tile '%s' at %s side ...",
-      verilog_fpath.c_str(), phy_block_type->name, side_manager.c_str());
+      verilog_fpath.c_str(), phy_block_type->name.c_str(),
+      side_manager.c_str());
   } else {
     VTR_LOG("Writing Verilog Netlist '%s' for physical_tile '%s'...",
-            verilog_fpath.c_str(), phy_block_type->name);
+            verilog_fpath.c_str(), phy_block_type->name.c_str());
   }
 
   /* Create the file stream */

openfpga/src/repack/lb_router.cpp

@@ -441,7 +441,7 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
       VTR_LOG(
         "Net %lu '%s' is impossible to route within proposed %s cluster\n",
         inet, atom_nlist.net_name(lb_net_atom_net_ids_[NetId(inet)]).c_str(),
-        lb_type_->name);
+        lb_type_->name.c_str());
       VTR_LOG("\tNet source pin:\n");
       for (size_t isrc = 0; isrc < lb_net_sources_[NetId(inet)].size();
            ++isrc) {

openfpga/src/tile_direct/build_tile_direct.cpp

@@ -355,8 +355,9 @@ static void report_direct_from_port_and_to_port_mismatch(
     "From_port '%s[%lu:%lu] of direct '%s' does not match to_port "
     "'%s[%lu:%lu]'!\n",
     from_tile_port.get_name().c_str(), from_tile_port.get_lsb(),
-    from_tile_port.get_msb(), vpr_direct.name, to_tile_port.get_name().c_str(),
-    to_tile_port.get_lsb(), to_tile_port.get_msb());
+    from_tile_port.get_msb(), vpr_direct.name.c_str(),
+    to_tile_port.get_name().c_str(), to_tile_port.get_lsb(),
+    to_tile_port.get_msb());
 }
 
 /***************************************************************************************
@@ -794,28 +795,29 @@ TileDirect build_device_tile_direct(const DeviceContext& device_ctx,
   TileDirect tile_direct;
 
   /* Walk through each direct definition in the VPR arch */
-  for (int idirect = 0; idirect < device_ctx.arch->num_directs; ++idirect) {
+  for (size_t idirect = 0; idirect < device_ctx.arch->directs.size();
+       ++idirect) {
     ArchDirectId arch_direct_id =
-      arch_direct.direct(std::string(device_ctx.arch->Directs[idirect].name));
+      arch_direct.direct(std::string(device_ctx.arch->directs[idirect].name));
     if (ArchDirectId::INVALID() == arch_direct_id) {
       VTR_LOG_ERROR(
         "Unable to find an annotation in openfpga architecture XML for "
         "<direct> '%s'!\n",
-        device_ctx.arch->Directs[idirect].name);
+        device_ctx.arch->directs[idirect].name.c_str());
       exit(1);
     }
     /* Build from original VPR arch definition */
     if (e_direct_type::INNER_COLUMN_OR_ROW ==
         arch_direct.type(arch_direct_id)) {
       build_inner_column_row_tile_direct(tile_direct,
-                                         device_ctx.arch->Directs[idirect],
+                                         device_ctx.arch->directs[idirect],
                                          device_ctx, arch_direct_id, verbose);
       /* Skip those direct connections which belong part of a connection block
        */
     }
     /* Build from OpenFPGA arch definition */
     build_inter_column_row_tile_direct(
-      tile_direct, device_ctx.arch->Directs[idirect], device_ctx, arch_direct,
+      tile_direct, device_ctx.arch->directs[idirect], device_ctx, arch_direct,
       arch_direct_id, verbose);
   }
 

openfpga/src/utils/check_tile_annotation.cpp

@@ -181,7 +181,7 @@ static int check_tile_annotation_conflicts_with_physical_tile(
                 required_tile_port.get_name().c_str(),
                 required_tile_port.get_lsb(), required_tile_port.get_msb(),
                 tile_annotation.global_port_name(tile_global_port).c_str(),
-                physical_tile.name, tile_port.name);
+                physical_tile.name.c_str(), tile_port.name);
               num_err++;
             }
 
@@ -196,7 +196,7 @@ static int check_tile_annotation_conflicts_with_physical_tile(
                 required_tile_port.get_name().c_str(),
                 required_tile_port.get_lsb(), required_tile_port.get_msb(),
                 tile_annotation.global_port_name(tile_global_port).c_str(),
-                physical_tile.name, tile_port.name);
+                physical_tile.name.c_str(), tile_port.name);
               num_err++;
             }
 
@@ -211,7 +211,7 @@ static int check_tile_annotation_conflicts_with_physical_tile(
                 required_tile_port.get_name().c_str(),
                 required_tile_port.get_lsb(), required_tile_port.get_msb(),
                 tile_annotation.global_port_name(tile_global_port).c_str(),
-                physical_tile.name, tile_port.name, pin_Fc);
+                physical_tile.name.c_str(), tile_port.name, pin_Fc);
             }
 
             found_matched_physical_tile_port++;

openfpga/src/utils/openfpga_physical_tile_utils.cpp

@@ -72,7 +72,7 @@ float find_physical_tile_pin_Fc(t_physical_tile_type_ptr type, const int& pin) {
   }
   /* Every pin should have a Fc, give a wrong value */
   VTR_LOGF_ERROR(__FILE__, __LINE__, "Fail to find the Fc for %s.pin[%lu]\n",
-                 type->name, pin);
+                 type->name.c_str(), pin);
   exit(1);
 }
 

openfpga_flow/scripts/run_fpga_flow.py

@@ -1017,17 +1017,17 @@ def run_command(taskname, logfile, command, exit_if_fail=True):
         try:
             output.write(" ".join(command) + "\n")
             process = subprocess.run(
-                command, stdout=subprocess.PIPE, stderr=subprocess.PIPE, universal_newlines=True
+                command, stdout=subprocess.PIPE, stderr=subprocess.PIPE, universal_newlines=False
             )
-            output.write(process.stdout)
-            output.write(process.stderr)
+            output.write(process.stdout.decode("cp1252"))
+            output.write(process.stderr.decode("cp1252"))
             output.write(str(process.returncode))
             if "openfpgashell" in logfile:
-                filter_openfpga_output(process.stdout)
+                filter_openfpga_output(process.stdout.decode("cp1252"))
             if process.returncode:
                 logger.error("%s run failed with returncode %d" % (taskname, process.returncode))
                 logger.error("command %s" % " ".join(command))
-                filter_failed_process_output(process.stderr)
+                filter_failed_process_output(process.stderr.decode("cp1252"))
                 if exit_if_fail:
                     clean_up_and_exit("Failed to run %s task" % taskname)
         except Exception:
@@ -1036,7 +1036,7 @@ def run_command(taskname, logfile, command, exit_if_fail=True):
             if exit_if_fail:
                 clean_up_and_exit("Failed to run %s task" % taskname)
     logger.info("%s is written in file %s" % (taskname, logfile))
-    return process.stdout
+    return process.stdout.decode("cp1252")
 
 
 def filter_openfpga_output(vpr_output):

openfpga_flow/scripts/run_fpga_task.py

@@ -542,7 +542,7 @@ def strip_child_logger_info(line):
 
 def run_single_script(s, eachJob, job_list):
     with s:
-        thread_name = threading.currentThread().getName()
+        thread_name = threading.current_thread().name
         eachJob["starttime"] = time.time()
         try:
             logfile = "%s_out.log" % thread_name

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf

@@ -53,6 +53,8 @@ bench1_openfpga_vpr_route_chan_width=44
 
 bench2_top = rst_and_clk_on_lut
 bench2_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_and_clk.xml
+# Triggered a bug in VPR, when route_chan_width=40, it failed
+bench2_openfpga_vpr_route_chan_width=44
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=

openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v

@@ -47,7 +47,7 @@ module and2_top_formal_verification_random_tb;
 	initial begin
 		clk[0] <= 1'b0;
 		while(1) begin
-			#0.809066534
+			#0.4880859554
 			clk[0] <= !clk[0];
 		end
 	end
@@ -106,7 +106,7 @@ initial begin
 	$timeformat(-9, 2, "ns", 20);
 	$display("Simulation start");
 // ----- Can be changed by the user for his/her need -------
-	#11.32693195
+	#6.833203316
 	if(nb_error == 0) begin
 		$display("Simulation Succeed");
 	end else begin