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setup pytest
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mbtaylor1982 committed Sep 6, 2023
1 parent fbcb410 commit 0f4ff9f
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Showing 4 changed files with 23 additions and 6 deletions.
8 changes: 4 additions & 4 deletions .vscode/tasks.json
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Expand Up @@ -24,7 +24,7 @@
"severity": 1,
"message": 3,
"file": 4,
"line": 5
"line": 5
}
},
"group": {
Expand All @@ -35,12 +35,12 @@
{
"label": "Run Testbench",
"type": "shell",
"command": "docker run --rm -v ${pwd}:/test -w /test -it mbtaylor1982/cocotb-iverilog:latest ./makefile",
"command": "docker run --rm -v ${pwd}:/test -w /test/RTL/cocotb/ -it mbtaylor1982/cocotb-iverilog:latest pytest",//./makefile",
"detail": "Run Testbench",
"presentation": {
"echo": true,
"reveal": "silent",
"focus": false,
"reveal": "always",
"focus": true,
"panel": "dedicated",
"showReuseMessage": false,
"clear": true
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Expand Up @@ -36,6 +36,6 @@ async def fifo_3bit_cntr_test(dut):


await RisingEdge(dut.CLK)
assert dut.COUNT.value == 1, "output COUNT did not return to zero"
assert dut.COUNT.value == 0, "output COUNT did not return to zero"


17 changes: 17 additions & 0 deletions RTL/cocotb/test_counter.py
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@@ -0,0 +1,17 @@
from cocotb_test.simulator import run
import pytest
import os
import cocotb

hdl_dir = os.path.dirname(__file__)

def test_ounter():
run(
toplevel_lang="verilog",
verilog_sources=[os.path.join("/test/RTL/FIFO/", "fifo_3bit_cntr.v")],
toplevel="fifo_3bit_cntr", # top level HDL
module="cocotb_fifo_3bit_cntr", # name of cocotb test module
python_search=[hdl_dir],
timescale="1ns/100ps",
force_compile="True"
)
2 changes: 1 addition & 1 deletion makefile
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Expand Up @@ -6,5 +6,5 @@ PWD=$(shell pwd)
export PYTHONPATH := $(PWD)/RTL/cocotb:$(PYTHONPATH)
VERILOG_SOURCES += $(PWD)/RTL/FIFO/fifo_3bit_cntr.v
TOPLEVEL = fifo_3bit_cntr
MODULE = test_fifo_3bit_cntr
MODULE = cocotb_fifo_3bit_cntr
include $(shell cocotb-config --makefiles)/Makefile.sim

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