fix test workflow

mbtaylor1982 · Aug 31, 2023 · 6af2a72 · 6af2a72
1 parent 19a7b1a
commit 6af2a72
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml
@@ -13,7 +13,7 @@ on:
       - '**.md'
 
 jobs:
-  synthesis:
+  testing:
     runs-on: ubuntu-latest
     container: hdlc/iverilog:latest
     steps:
@@ -23,6 +23,6 @@ jobs:
       # 2 - Run TestBench 
       - name: Run testbench
         run: |
-            iverilog   -o RTL\build\RESDMAC_DMA_SCSI_READ_CYCLE_tb.v.out RTL\TestBench\RESDMAC_DMA_SCSI_READ_CYCLE_tb.v 
+            iverilog   -o RTL/build/RESDMAC_DMA_SCSI_READ_CYCLE_tb.v.out RTL/TestBench/RESDMAC_DMA_SCSI_READ_CYCLE_tb.v 
             vvp RESDMAC_DMA_SCSI_READ_CYCLE_tb.v.out