Add case for no buffers

meiniKi · Apr 3, 2024 · 4925b82 · 4925b82
1 parent 5dc5b2c
commit 4925b82
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Showing 2 changed files with 6 additions and 2 deletions.
diff --git a/rtl/fazyrv_pc.sv b/rtl/fazyrv_pc.sv
@@ -104,8 +104,10 @@ assign carry_vec[0] = carry_r[0];
 logic [31:0] pc_dlyd;
 `ifdef SKY130
   sky130_fd_sc_hd__dlygate4sd3_1 i_buf[31:0] ( .X(pc_dlyd), .A(pc_r) );
-`else
+`elsif SIM
   buf #1 i_buf[31:0] (pc_dlyd, pc_r);
+`else
+  assign pc_dlyd = pc_r; 
 `endif
 
 assign pc_n = shift_i ? {din_i, pc_dlyd[31:CHUNKSIZE]} : pc_dlyd;

diff --git a/rtl/fazyrv_shftreg.sv b/rtl/fazyrv_shftreg.sv
@@ -43,8 +43,10 @@ logic [31:0] reg_r;
 logic [31-CHUNKSIZE:0] reg_dlyd;
 `ifdef SKY130
   sky130_fd_sc_hd__dlygate4sd3_1 i_buf[31-CHUNKSIZE:0] ( .X(reg_dlyd), .A(reg_r[31:CHUNKSIZE]) );
-`else
+`elsif SIM
   buf #1 i_buf[31-CHUNKSIZE:0] (reg_dlyd, reg_r[31:CHUNKSIZE]);
+`else
+  assign reg_dlyd = reg_r[31:CHUNKSIZE];
 `endif
 
 assign dat_o = reg_r[CHUNKSIZE-1:0];