Skip to content
CI

Add SS2-style iCE40 AES FPGA target. #609

Sign in to view logs

Add SS2-style iCE40 AES FPGA target.

Add SS2-style iCE40 AES FPGA target. #609

Run time

Learn about OS pricing on GitHub Actions
Job Run time
Lint code base using mypy (and pylint in future)
1m 1s
1m 1s