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align to new DPPI API
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e-rk committed Oct 16, 2024
1 parent 1089519 commit 18e4a1a
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Showing 22 changed files with 82 additions and 34 deletions.
18 changes: 10 additions & 8 deletions applications/nrf5340_audio/src/modules/audio_sync_timer.c
Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,8 @@ static uint8_t dppi_channel_timer_sync_with_rtc;
static uint8_t dppi_channel_rtc_start;
static volatile uint32_t num_rtc_overflows;

static nrfx_dppi_t dppi = NRFX_DPPI_INSTANCE(0);

static nrfx_timer_config_t cfg = {.frequency = NRFX_MHZ_TO_HZ(1UL),
.mode = NRF_TIMER_MODE_TIMER,
.bit_width = NRF_TIMER_BIT_WIDTH_32,
Expand Down Expand Up @@ -161,7 +163,7 @@ static int audio_sync_timer_init(void)
nrfx_rtc_overflow_enable(&audio_sync_lf_timer_instance, true);

/* Initialize capturing of I2S frame start event timestamps */
ret = nrfx_dppi_channel_alloc(&dppi_channel_i2s_frame_start);
ret = nrfx_dppi_channel_alloc(&dppi, &dppi_channel_i2s_frame_start);
if (ret - NRFX_ERROR_BASE_NUM) {
LOG_ERR("nrfx DPPI channel alloc error (I2S frame start): %d", ret);
return -ENOMEM;
Expand All @@ -177,14 +179,14 @@ static int audio_sync_timer_init(void)
dppi_channel_i2s_frame_start);

nrf_i2s_publish_set(NRF_I2S0, NRF_I2S_EVENT_FRAMESTART, dppi_channel_i2s_frame_start);
ret = nrfx_dppi_channel_enable(dppi_channel_i2s_frame_start);
ret = nrfx_dppi_channel_enable(&dppi, dppi_channel_i2s_frame_start);
if (ret - NRFX_ERROR_BASE_NUM) {
LOG_ERR("nrfx DPPI channel enable error (I2S frame start): %d", ret);
return -EIO;
}

/* Initialize capturing of current timestamps */
ret = nrfx_dppi_channel_alloc(&dppi_channel_curr_time_capture);
ret = nrfx_dppi_channel_alloc(&dppi, &dppi_channel_curr_time_capture);
if (ret - NRFX_ERROR_BASE_NUM) {
LOG_ERR("nrfx DPPI channel alloc error (I2S frame start) - Return value: %d", ret);
return -ENOMEM;
Expand All @@ -200,14 +202,14 @@ static int audio_sync_timer_init(void)

nrf_egu_publish_set(NRF_EGU0, NRF_EGU_EVENT_TRIGGERED0, dppi_channel_curr_time_capture);

ret = nrfx_dppi_channel_enable(dppi_channel_curr_time_capture);
ret = nrfx_dppi_channel_enable(&dppi, dppi_channel_curr_time_capture);
if (ret - NRFX_ERROR_BASE_NUM) {
LOG_ERR("nrfx DPPI channel enable error (I2S frame start) - Return value: %d", ret);
return -EIO;
}

/* Initialize functionality for synchronization between APP and NET core */
ret = nrfx_dppi_channel_alloc(&dppi_channel_rtc_start);
ret = nrfx_dppi_channel_alloc(&dppi, &dppi_channel_rtc_start);
if (ret - NRFX_ERROR_BASE_NUM) {
LOG_ERR("nrfx DPPI channel alloc error (timer clear): %d", ret);
return -ENOMEM;
Expand All @@ -222,14 +224,14 @@ static int audio_sync_timer_init(void)
NRF_IPC_CHANNEL_4);
nrf_ipc_publish_set(NRF_IPC, AUDIO_SYNC_TIMER_NET_APP_IPC_EVT, dppi_channel_rtc_start);

ret = nrfx_dppi_channel_enable(dppi_channel_rtc_start);
ret = nrfx_dppi_channel_enable(&dppi, dppi_channel_rtc_start);
if (ret - NRFX_ERROR_BASE_NUM) {
LOG_ERR("nrfx DPPI channel enable error (timer clear): %d", ret);
return -EIO;
}

/* Initialize functionality for synchronization between RTC and TIMER */
ret = nrfx_dppi_channel_alloc(&dppi_channel_timer_sync_with_rtc);
ret = nrfx_dppi_channel_alloc(&dppi, &dppi_channel_timer_sync_with_rtc);
if (ret - NRFX_ERROR_BASE_NUM) {
LOG_ERR("nrfx DPPI channel alloc error (timer clear): %d", ret);
return -ENOMEM;
Expand All @@ -242,7 +244,7 @@ static int audio_sync_timer_init(void)

nrfx_rtc_tick_enable(&audio_sync_lf_timer_instance, false);

ret = nrfx_dppi_channel_enable(dppi_channel_timer_sync_with_rtc);
ret = nrfx_dppi_channel_enable(&dppi, dppi_channel_timer_sync_with_rtc);
if (ret - NRFX_ERROR_BASE_NUM) {
LOG_ERR("nrfx DPPI channel enable error (timer clear): %d", ret);
return -EIO;
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -6,4 +6,4 @@

CONFIG_NRFX_TIMER0=y
CONFIG_NRFX_RTC0=y
CONFIG_NRFX_DPPI=y
CONFIG_NRFX_DPPI0=y
Original file line number Diff line number Diff line change
Expand Up @@ -6,4 +6,4 @@

CONFIG_NRFX_TIMER0=y
CONFIG_NRFX_RTC0=y
CONFIG_NRFX_DPPI=y
CONFIG_NRFX_DPPI0=y
Original file line number Diff line number Diff line change
Expand Up @@ -4,5 +4,8 @@
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
#

CONFIG_NRFX_DPPI=y
CONFIG_NRFX_DPPI00=y
CONFIG_NRFX_DPPI10=y
CONFIG_NRFX_DPPI20=y
CONFIG_NRFX_DPPI30=y
CONFIG_BT_RX_STACK_SIZE=2048
Original file line number Diff line number Diff line change
Expand Up @@ -4,5 +4,8 @@
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
#

CONFIG_NRFX_DPPI=y
CONFIG_NRFX_DPPI00=y
CONFIG_NRFX_DPPI10=y
CONFIG_NRFX_DPPI20=y
CONFIG_NRFX_DPPI30=y
CONFIG_BT_RX_STACK_SIZE=2048
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,6 @@ CONFIG_IPC_SERVICE=y
CONFIG_IPC_SERVICE_BACKEND_RPMSG=y
CONFIG_MBOX=y

CONFIG_NRFX_DPPI=y
CONFIG_NRFX_DPPI0=y

CONFIG_HEAP_MEM_POOL_SIZE=4096
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ CONFIG_IPC_SERVICE=y
CONFIG_IPC_SERVICE_BACKEND_RPMSG=y
CONFIG_MBOX=y

CONFIG_NRFX_DPPI=y
CONFIG_NRFX_DPPI0=y

CONFIG_HEAP_MEM_POOL_SIZE=4096

Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -12,4 +12,7 @@ CONFIG_NRFX_TIMER2=n
# Use necessary peripherals
CONFIG_NRFX_TIMER20=y
CONFIG_NRFX_TIMER10=y
CONFIG_NRFX_DPPI=y
CONFIG_NRFX_DPPI00=y
CONFIG_NRFX_DPPI10=y
CONFIG_NRFX_DPPI20=y
CONFIG_NRFX_DPPI30=y
Original file line number Diff line number Diff line change
Expand Up @@ -12,4 +12,7 @@ CONFIG_NRFX_TIMER2=n
# Use necessary peripherals
CONFIG_NRFX_TIMER20=y
CONFIG_NRFX_TIMER10=y
CONFIG_NRFX_DPPI=y
CONFIG_NRFX_DPPI00=y
CONFIG_NRFX_DPPI10=y
CONFIG_NRFX_DPPI20=y
CONFIG_NRFX_DPPI30=y
Original file line number Diff line number Diff line change
Expand Up @@ -6,4 +6,4 @@

CONFIG_NRFX_TIMER0=y
CONFIG_NRFX_RTC0=y
CONFIG_NRFX_DPPI=y
CONFIG_NRFX_DPPI0=y
Original file line number Diff line number Diff line change
Expand Up @@ -6,4 +6,4 @@

CONFIG_NRFX_TIMER0=y
CONFIG_NRFX_RTC0=y
CONFIG_NRFX_DPPI=y
CONFIG_NRFX_DPPI0=y
Original file line number Diff line number Diff line change
Expand Up @@ -4,5 +4,8 @@
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
#

CONFIG_NRFX_DPPI=y
CONFIG_NRFX_DPPI00=y
CONFIG_NRFX_DPPI10=y
CONFIG_NRFX_DPPI20=y
CONFIG_NRFX_DPPI30=y
CONFIG_BT_RX_STACK_SIZE=2048
Original file line number Diff line number Diff line change
Expand Up @@ -4,5 +4,8 @@
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
#

CONFIG_NRFX_DPPI=y
CONFIG_NRFX_DPPI00=y
CONFIG_NRFX_DPPI10=y
CONFIG_NRFX_DPPI20=y
CONFIG_NRFX_DPPI30=y
CONFIG_BT_RX_STACK_SIZE=2048
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,11 @@ CONFIG_PTT_CACHE_MGMT=n

# nrfx drivers configuration:
CONFIG_NRFX_TIMER20=y # enable TIMER2
CONFIG_NRFX_DPPI=y # enable DPPIC
# enable DPPIC
CONFIG_NRFX_DPPI00=y
CONFIG_NRFX_DPPI10=y
CONFIG_NRFX_DPPI20=y
CONFIG_NRFX_DPPI30=y

# Set temperature sensor update period in ms
CONFIG_NRF_802154_TEMPERATURE_UPDATE_PERIOD=10000
Original file line number Diff line number Diff line change
Expand Up @@ -9,4 +9,7 @@ CONFIG_NRFX_TIMER0=n

# Enable the necessary drivers
CONFIG_NRFX_TIMER10=y
CONFIG_NRFX_DPPI=y
CONFIG_NRFX_DPPI00=y
CONFIG_NRFX_DPPI10=y
CONFIG_NRFX_DPPI20=y
CONFIG_NRFX_DPPI30=y
Original file line number Diff line number Diff line change
Expand Up @@ -9,4 +9,7 @@ CONFIG_NRFX_TIMER0=n

# Enable the necessary drivers
CONFIG_NRFX_TIMER10=y
CONFIG_NRFX_DPPI=y
CONFIG_NRFX_DPPI00=y
CONFIG_NRFX_DPPI10=y
CONFIG_NRFX_DPPI20=y
CONFIG_NRFX_DPPI30=y
7 changes: 5 additions & 2 deletions subsys/debug/cpu_load/cpu_load.c
Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,9 @@ static uint32_t shared_ch_mask;
(IS_ENABLED(CONFIG_CPU_LOAD_USE_SHARED_DPPI_CHANNELS) && \
(BIT(ch) & shared_ch_mask))

#ifdef DPPI_PRESENT
static nrfx_dppi_t dppi = NRFX_DPPI_INSTANCE(0);
#endif

/** @brief Allocate (D)PPI channel. */
static nrfx_err_t ppi_alloc(uint8_t *ch, uint32_t evt)
Expand All @@ -60,7 +63,7 @@ static nrfx_err_t ppi_alloc(uint8_t *ch, uint32_t evt)
err = NRFX_SUCCESS;
shared_ch_mask |= BIT(*ch);
} else {
err = nrfx_dppi_channel_alloc(ch);
err = nrfx_dppi_channel_alloc(&dppi, ch);
}
#else
err = nrfx_ppi_channel_alloc((nrf_ppi_channel_t *)ch);
Expand All @@ -73,7 +76,7 @@ static nrfx_err_t ppi_free(uint8_t ch)
#ifdef DPPI_PRESENT
if (!IS_ENABLED(CONFIG_CPU_LOAD_USE_SHARED_DPPI_CHANNELS)
|| ((BIT(ch) & shared_ch_mask) == 0)) {
return nrfx_dppi_channel_free(ch);
return nrfx_dppi_channel_free(&dppi, ch);
} else {
return NRFX_SUCCESS;
}
Expand Down
6 changes: 5 additions & 1 deletion subsys/debug/ppi_trace/ppi_trace.c
Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,10 @@ LOG_MODULE_REGISTER(ppi_trace, CONFIG_PPI_TRACE_LOG_LEVEL);
[DT_PROP(gpio_node, port)] = \
NRFX_GPIOTE_INSTANCE(DT_PROP(GPIOTE_NODE(gpio_node), instance)),

#ifdef DPPI_PRESENT
static nrfx_dppi_t dppi = NRFX_DPPI_INSTANCE(0);
#endif

static const nrfx_gpiote_t *get_gpiote(nrfx_gpiote_pin_t pin)
{
static const nrfx_gpiote_t gpiote[GPIO_COUNT] = {
Expand All @@ -73,7 +77,7 @@ static nrfx_err_t ppi_alloc(uint8_t *ch, uint32_t evt)
*ch = *PUBLISH_ADDR(evt) & DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk;
err = NRFX_SUCCESS;
} else {
err = nrfx_dppi_channel_alloc(ch);
err = nrfx_dppi_channel_alloc(&dppi, ch);
}
#else
err = nrfx_ppi_channel_alloc((nrf_ppi_channel_t *)ch);
Expand Down
5 changes: 4 additions & 1 deletion subsys/dm/dm.c
Original file line number Diff line number Diff line change
Expand Up @@ -25,8 +25,11 @@

#if defined(DPPI_PRESENT)
#include <nrfx_dppi.h>

static nrfx_dppi_t dppi = NRFX_DPPI_INSTANCE(0);

#define gppi_channel_t uint8_t
#define gppi_channel_alloc nrfx_dppi_channel_alloc
#define gppi_channel_alloc(x) nrfx_dppi_channel_alloc(&dppi, x)
#else
#include <nrfx_ppi.h>
#define gppi_channel_t nrf_ppi_channel_t
Expand Down
6 changes: 5 additions & 1 deletion subsys/mpsl/fem/common/mpsl_fem_utils.c
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,10 @@
#include <nrfx_dppi.h>
#endif

#ifdef DPPI_PRESENT
static nrfx_dppi_t dppi = NRFX_DPPI_INSTANCE(0);
#endif

int mpsl_fem_utils_ppi_channel_alloc(uint8_t *ppi_channels, size_t size)
{
nrfx_err_t err = NRFX_ERROR_NOT_SUPPORTED;
Expand All @@ -24,7 +28,7 @@ int mpsl_fem_utils_ppi_channel_alloc(uint8_t *ppi_channels, size_t size)
IF_ENABLED(CONFIG_HAS_HW_NRF_PPI,
(err = nrfx_ppi_channel_alloc(&ppi_channels[i]);));
IF_ENABLED(CONFIG_HAS_HW_NRF_DPPIC,
(err = nrfx_dppi_channel_alloc(&ppi_channels[i]);));
(err = nrfx_dppi_channel_alloc(&dppi, &ppi_channels[i]);));
if (err != NRFX_SUCCESS) {
return -ENOMEM;
}
Expand Down
10 changes: 6 additions & 4 deletions subsys/mpsl/pin_debug/mpsl_pin_debug_radio_core.c
Original file line number Diff line number Diff line change
Expand Up @@ -103,12 +103,14 @@ static int m_ppi_config(void)
uint8_t dppi_chan_ready_disabled;
uint8_t dppi_chan_address_end;

if (nrfx_dppi_channel_alloc(&dppi_chan_ready_disabled) != NRFX_SUCCESS) {
nrfx_dppi_t dppi = NRFX_DPPI_INSTANCE(0);

if (nrfx_dppi_channel_alloc(&dppi, &dppi_chan_ready_disabled) != NRFX_SUCCESS) {
LOG_ERR("Failed allocating DPPI chan");
return -ENOMEM;
}

if (nrfx_dppi_channel_alloc(&dppi_chan_address_end) != NRFX_SUCCESS) {
if (nrfx_dppi_channel_alloc(&dppi, &dppi_chan_address_end) != NRFX_SUCCESS) {
LOG_ERR("Failed allocating DPPI chan");
return -ENOMEM;
}
Expand All @@ -132,12 +134,12 @@ static int m_ppi_config(void)
nrfx_gpiote_out_task_address_get(&gpiote,
CONFIG_MPSL_PIN_DEBUG_RADIO_ADDRESS_AND_END_PIN));

if (nrfx_dppi_channel_enable(dppi_chan_ready_disabled) != NRFX_SUCCESS) {
if (nrfx_dppi_channel_enable(&dppi, dppi_chan_ready_disabled) != NRFX_SUCCESS) {
LOG_ERR("Failed enabling channel");
return -ENOMEM;
}

if (nrfx_dppi_channel_enable(dppi_chan_address_end) != NRFX_SUCCESS) {
if (nrfx_dppi_channel_enable(&dppi, dppi_chan_address_end) != NRFX_SUCCESS) {
LOG_ERR("Failed enabling channel");
return -ENOMEM;
}
Expand Down
6 changes: 4 additions & 2 deletions tests/subsys/debug/cpu_load/src/test_cpu_load.c
Original file line number Diff line number Diff line change
Expand Up @@ -46,10 +46,12 @@ ZTEST(cpu_load, test_cpu_load)
config.frequency = NRFX_MHZ_TO_HZ(1);
config.bit_width = NRF_TIMER_BIT_WIDTH_32;

nrfx_dppi_t dppi = NRFX_DPPI_INSTANCE(0);

err = nrfx_timer_init(&timer, &config, timer_handler);
zassert_equal(err, NRFX_SUCCESS, "Unexpected error:%d", err);

err = nrfx_dppi_channel_alloc(&ch);
err = nrfx_dppi_channel_alloc(&dppi, &ch);
zassert_equal(err, NRFX_SUCCESS, "Unexpected error:%d", err);

nrfx_gppi_channel_endpoints_setup(ch, evt, tsk);
Expand All @@ -62,7 +64,7 @@ ZTEST(cpu_load, test_cpu_load)
nrfx_gppi_channels_disable(BIT(ch));
nrfx_gppi_event_endpoint_clear(ch, evt);
nrfx_gppi_task_endpoint_clear(ch, tsk);
err = nrfx_dppi_channel_free(ch);
err = nrfx_dppi_channel_free(&dppi, ch);
}
#endif

Expand Down

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