tests: benchmarks: multicore: add idle_clock_control

tests/benchmarks/multicore/idle_clock_control/CMakeLists.txt

@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+if(NOT SYSBUILD)
+	message(FATAL_ERROR
+		" This is a multi-image application that should be built using sysbuild.\n"
+		" Add --sysbuild argument to west build command to prepare all the images.")
+endif()
+
+project(idle_clock_control)
+
+target_sources(app PRIVATE src/main.c)

tests/benchmarks/multicore/idle_clock_control/Kconfig.sysbuild

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+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+source "${ZEPHYR_BASE}/share/sysbuild/Kconfig"
+
+config REMOTE_BOARD
+	string "The board used for remote target"

tests/benchmarks/multicore/idle_clock_control/prj.conf

@@ -0,0 +1,21 @@
+CONFIG_PM=y
+CONFIG_PM_S2RAM=y
+CONFIG_PM_S2RAM_CUSTOM_MARKING=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_DEVICE_RUNTIME=y
+CONFIG_POWEROFF=y
+
+CONFIG_GPIO=n
+CONFIG_BOOT_BANNER=n
+CONFIG_SOC_NRF54H20_NO_MRAM_LATENCY=n
+
+CONFIG_NRFS=y
+CONFIG_CLOCK_CONTROL=y
+CONFIG_ASSERT=y
+
+# Enable for debugging purposes only
+CONFIG_PRINTK=n
+CONFIG_LOG=n
+CONFIG_CONSOLE=n
+CONFIG_UART_CONSOLE=n
+CONFIG_SERIAL=n

tests/benchmarks/multicore/idle_clock_control/remote/CMakeLists.txt

@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(remote)
+
+target_sources(app PRIVATE src/main.c)

tests/benchmarks/multicore/idle_clock_control/remote/prj.conf

@@ -0,0 +1,8 @@
+CONFIG_PM=y
+CONFIG_POWEROFF=y
+CONFIG_CONSOLE=n
+CONFIG_UART_CONSOLE=n
+CONFIG_SERIAL=n
+CONFIG_GPIO=n
+CONFIG_BOOT_BANNER=n
+CONFIG_SOC_NRF54H20_NO_MRAM_LATENCY=n

tests/benchmarks/multicore/idle_clock_control/remote/src/main.c

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+#include <zephyr/kernel.h>
+
+int main(void)
+{
+	k_sleep(K_FOREVER);
+
+	return 0;
+}

tests/benchmarks/multicore/idle_clock_control/src/main.c

@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/sys/printk.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/devicetree/clocks.h>
+#include <zephyr/drivers/clock_control/nrf_clock_control.h>
+
+LOG_MODULE_REGISTER(idle_clock_control);
+
+struct test_clk_ctx {
+	const struct device *clk_dev;
+	const struct nrf_clock_spec *clk_specs;
+	size_t clk_specs_size;
+};
+
+const struct nrf_clock_spec test_clk_specs_hsfll[] = {
+	{
+		.frequency = MHZ(128),
+		.accuracy = 0,
+		.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
+	},
+	{
+		.frequency = MHZ(320),
+		.accuracy = 0,
+		.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
+	},
+	{
+		.frequency = MHZ(64),
+		.accuracy = 0,
+		.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
+	},
+};
+
+const struct nrf_clock_spec test_clk_specs_fll16m[] = {
+	{
+		.frequency = MHZ(16),
+		.accuracy = 20000,
+		.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
+	},
+	{
+		.frequency = MHZ(16),
+		.accuracy = 5020,
+		.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
+	},
+	{
+		.frequency = MHZ(16),
+		.accuracy = 30,
+		.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
+	},
+};
+
+static const struct test_clk_ctx fll16m_test_clk_ctx[] = {
+	{
+		.clk_dev = DEVICE_DT_GET(DT_NODELABEL(fll16m)),
+		.clk_specs = test_clk_specs_fll16m,
+		.clk_specs_size = ARRAY_SIZE(test_clk_specs_fll16m),
+	},
+};
+
+static const struct test_clk_ctx hsfll_test_clk_ctx[] = {
+	{
+		.clk_dev = DEVICE_DT_GET(DT_NODELABEL(cpuapp_hsfll)),
+		.clk_specs = test_clk_specs_hsfll,
+		.clk_specs_size = ARRAY_SIZE(test_clk_specs_hsfll),
+	},
+};
+
+const struct nrf_clock_spec test_clk_specs_lfclk[] = {
+	{
+		.frequency = 32768,
+		.accuracy = 0,
+		.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
+	},
+	{
+		.frequency = 32768,
+		.accuracy = 20,
+		.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
+	},
+	{
+		.frequency = 32768,
+		.accuracy = 20,
+		.precision = NRF_CLOCK_CONTROL_PRECISION_HIGH,
+	},
+};
+
+static const struct test_clk_ctx lfclk_test_clk_ctx[] = {
+	{
+		.clk_dev = DEVICE_DT_GET(DT_NODELABEL(lfclk)),
+		.clk_specs = test_clk_specs_lfclk,
+		.clk_specs_size = ARRAY_SIZE(test_clk_specs_lfclk),
+	},
+};
+
+static void test_request_release_clock_spec(const struct device *clk_dev,
+					    const struct nrf_clock_spec *clk_spec)
+{
+	int ret = 0;
+	int res = 0;
+	struct onoff_client cli;
+	uint32_t rate;
+
+	LOG_INF("Clock under test: %s", clk_dev->name);
+	sys_notify_init_spinwait(&cli.notify);
+	ret = nrf_clock_control_request(clk_dev, clk_spec, &cli);
+	__ASSERT_NO_MSG(ret == 0);
+	do {
+		ret = sys_notify_fetch_result(&cli.notify, &res);
+		k_yield();
+	} while (ret == -EAGAIN);
+	__ASSERT_NO_MSG(ret == 0);
+	__ASSERT_NO_MSG(res == 0);
+	ret = clock_control_get_rate(clk_dev, NULL, &rate);
+	__ASSERT_NO_MSG(ret == 0);
+	__ASSERT_NO_MSG(rate == clk_spec->frequency);
+	k_busy_wait(10000);
+	ret = nrf_clock_control_release(clk_dev, clk_spec);
+	__ASSERT_NO_MSG(ret == ONOFF_STATE_ON);
+}
+
+static void test_clock_control_request(const struct test_clk_ctx *clk_contexts,
+				       size_t contexts_size)
+{
+	const struct test_clk_ctx *clk_context;
+	size_t clk_specs_size;
+	const struct device *clk_dev;
+	const struct nrf_clock_spec *clk_spec;
+
+	for (size_t i = 0; i < contexts_size; i++) {
+		clk_context = &clk_contexts[i];
+		clk_specs_size = clk_context->clk_specs_size;
+
+		for (size_t u = 0; u < clk_specs_size; u++) {
+			clk_dev = clk_context->clk_dev;
+			clk_spec = &clk_context->clk_specs[u];
+
+			LOG_INF("Applying clock (%s) spec: frequency %d, accuracy %d, precision "
+				"%d",
+				clk_dev->name, clk_spec->frequency, clk_spec->accuracy,
+				clk_spec->precision);
+			test_request_release_clock_spec(clk_dev, clk_spec);
+			k_msleep(1000);
+		}
+	}
+}
+
+int main(void)
+{
+	LOG_INF("Idle clock_control, %s", CONFIG_BOARD_TARGET);
+	k_msleep(100);
+	while (1) {
+		test_clock_control_request(hsfll_test_clk_ctx, ARRAY_SIZE(hsfll_test_clk_ctx));
+		test_clock_control_request(fll16m_test_clk_ctx, ARRAY_SIZE(fll16m_test_clk_ctx));
+		test_clock_control_request(lfclk_test_clk_ctx, ARRAY_SIZE(lfclk_test_clk_ctx));
+	}
+
+	return 0;
+}

tests/benchmarks/multicore/idle_clock_control/sysbuild.cmake

@@ -0,0 +1,22 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+if("${SB_CONFIG_REMOTE_BOARD}" STREQUAL "")
+  message(FATAL_ERROR "REMOTE_BOARD must be set to a valid board name")
+endif()
+
+# Add remote project
+ExternalZephyrProject_Add(
+    APPLICATION remote
+    SOURCE_DIR ${APP_DIR}/remote
+    BOARD ${SB_CONFIG_REMOTE_BOARD}
+    BOARD_REVISION ${BOARD_REVISION}
+  )
+
+# Add a dependency so that the remote image will be built and flashed first
+add_dependencies(idle_clock_control remote)
+# Add dependency so that the remote image is flashed first.
+sysbuild_add_dependencies(FLASH idle_clock_control remote)

tests/benchmarks/multicore/idle_clock_control/sysbuild/nrf54h20dk_nrf54h20_cpurad.conf

@@ -0,0 +1 @@
+SB_CONFIG_REMOTE_BOARD="nrf54h20dk/nrf54h20/cpurad"

tests/benchmarks/multicore/idle_clock_control/testcase.yaml

@@ -0,0 +1,18 @@
+common:
+  sysbuild: true
+  tags: ci_build ci_tests_benchmarks_multicore ppk_power_measure
+
+tests:
+  benchmarks.multicore.idle_clock_control:
+    harness: pytest
+    platform_allow:
+      - nrf54h20dk/nrf54h20/cpuapp
+    integration_platforms:
+      - nrf54h20dk/nrf54h20/cpuapp
+    extra_args:
+      - SB_CONF_FILE=sysbuild/nrf54h20dk_nrf54h20_cpurad.conf
+    harness_config:
+      fixture: ppk_power_measure
+      pytest_root:
+        - "${CUSTOM_ROOT_TEST_DIR}/test_measure_power_consumption.py::test_measure_and_data_dump_power_consumption_clock_control"
+    timeout: 90