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[WIP DNM] x86: build cpukinds from AMD CPUID leaf 0x80000026 #587

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@bgoglin bgoglin commented May 12, 2023

Use coretype to build "AMD-ECore" and "AMD-Pcore" kinds.

Use power efficiency rankings to build kinds with native efficiencies.

Only tested on manually modified CPUID values. Merge this once tested on an actual platform. Likely soon since some code (in AMD Pstate driver) is under review.

Use coretype to build "AMD-ECore" and "AMD-Pcore" kinds.

Use power efficiency rankings to build kinds with native efficiencies.

Signed-off-by: Brice Goglin <[email protected]>
PPR says it's in core level, which means
we get the info from each thread?

Signed-off-by: Brice Goglin <[email protected]>
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bgoglin commented Sep 18, 2024

@superm1 thanks to your CPUID dump in #690, I was able to verify that this code mostly works:

CPU kind #0 efficiency -1 cpuset 0x00ff0ff0
  CoreType = AMD-ECore
CPU kind #1 efficiency -1 cpuset 0x0000f00f
  CoreType = AMD-PCore

Does this CPU report EfficiencyRanking? I see 1 in EfficiencyRankingAvailable=1 in the first level but the ranking I read is 0 for all cores (that's why I have "efficiency -1" (unknown) above).

Also, I am not sure I understand why AsymmetricTopology=1 only in the second level, EfficiencyRankingAvailable=1 only in first level (that one is documented), and HeterogeneousCores=1 in first 3 levels but not in 4th.

printf(" EffRankingAvailable = %u\n", (eax & 0x20000000)>>29);
printf(" CoreType = %u\n", (ebx >> 28) & 0xf);
printf(" Model = %u\n", (ebx >> 24) & 0xf);
printf(" EffRanking = %u\n", (ebx >> 16) & 0xff);
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Well, 0xf is 4 bits and 0xff is 8bits so all these look OK?

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superm1 commented Sep 18, 2024

Also, I am not sure I understand why AsymmetricTopology=1 only in the second level

It's a topology indicator only. IE how they're grouped into larger units. It's meant to be used in conjunction with bit 30 and 29. IE if it's "1" then software is supposed to discover more details from 30 and 29.

EfficiencyRankingAvailable=1 only in first level (that one is documented)

I think APM explains that already.

HeterogeneousCores=1 in first 3 levels but not in 4th

It's a single socket system.

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bgoglin commented Sep 19, 2024

@superm1 Is the "NativeModelId" CPUID info supposed to be the same for all cores on hybrid CPUs?
The doc says "This value is used by software to further differentiate implementation specific software visible properties between the cores". I am not sure if that applies to cores of different chips, or different cores of the same chip.

I couldn't find the PPR for Strix Point. In the 19h family PPR, I see "Zen4" as the only NativeModelID possible value. Could we see some hybrid CPUs return something like "Zen5" and "Zen5c" for different cores? Or will they all return "Zen5" while CoreType is the only field distinguishing between Ecore and Pcore?

By the way, in case you missed the question above:
Does this CPU report EfficiencyRanking? I see 1 in EfficiencyRankingAvailable=1 in the first level but the ranking I read is 0 for all cores (that's why I have "efficiency -1" (unknown) above).

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superm1 commented Sep 19, 2024

Yeah the publication of the docs sometimes lags a bit from the launch, sorry about that. I double checked though and 0h means Zen5 for NativeModelId on Strix. There is no differentiation of Zen5 vs Zen5c at this field. You would tell that from CoreType when called with the cpuid is called with level 1h (Core)

Does this CPU report EfficiencyRanking? I see 1 in EfficiencyRankingAvailable=1 in the first level but the ranking I read is 0 for all cores (that's why I have "efficiency -1" (unknown) above).

I guess not; but I'm not sure why. There are definitely rankings utilized from the CPPC MSRs.

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