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arm/scs: Rename SCS functions according to the naming convention
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JIRA: RTOS-886
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@agkaminski
agkaminski committed Oct 4, 2024
1 parent 6435836 commit a10f91b
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Showing 13 changed files with 89 additions and 89 deletions.
40 changes: 20 additions & 20 deletions hal/arm/scs.c
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Original file line number Diff line number Diff line change
Expand Up @@ -92,7 +92,7 @@ static struct {
} scs_common;


void _hal_nvicSetIRQ(s8 irqn, u8 state)
void _hal_scsIRQSet(s8 irqn, u8 state)
{
volatile u32 *ptr = (state != 0) ? scs_common.scs->iser : scs_common.scs->icer;

Expand All @@ -103,7 +103,7 @@ void _hal_nvicSetIRQ(s8 irqn, u8 state)
}


void _hal_nvicSetPriority(s8 irqn, u32 priority)
void _hal_scsIRQPrioritySet(s8 irqn, u32 priority)
{
volatile u8 *ptr = (volatile u8 *)scs_common.scs->ip;

Expand All @@ -114,7 +114,7 @@ void _hal_nvicSetPriority(s8 irqn, u32 priority)
}


void _hal_nvicSetPending(s8 irqn)
void _hal_scsIRQPendingSet(s8 irqn)
{
volatile u32 *ptr = scs_common.scs->ispr;

Expand All @@ -125,21 +125,21 @@ void _hal_nvicSetPending(s8 irqn)
}


int _hal_nvicGetPendingIRQ(s8 irqn)
int _hal_scsIRQPendingGet(s8 irqn)
{
volatile u32 *ptr = &scs_common.scs->ispr[(u8)irqn >> 5];
return ((*ptr & (1 << (irqn & 0x1f))) != 0) ? 1 : 0;
}


int _hal_nvicGetActive(s8 irqn)
int _hal_scsIRQActiveGet(s8 irqn)
{
volatile u32 *ptr = &scs_common.scs->iabr[(u8)irqn >> 5];
return ((*ptr & (1 << (irqn & 0x1f))) != 0) ? 1 : 0;
}


void _hal_scbSetPriorityGrouping(u32 group)
void _hal_scsPriorityGroupingSet(u32 group)
{
u32 t;

Expand All @@ -153,13 +153,13 @@ void _hal_scbSetPriorityGrouping(u32 group)
}


u32 _hal_scbGetPriorityGrouping(void)
u32 _hal_scsPriorityGroupingGet(void)
{
return (scs_common.scs->aircr & 0x700) >> 8;
}


void _hal_scbSetPriority(s8 excpn, u32 priority)
void _hal_scsExceptionPrioritySet(s8 excpn, u32 priority)
{
volatile u8 *ptr = (u8 *)&scs_common.scs->shpr1 + excpn - 4;

Expand All @@ -168,15 +168,15 @@ void _hal_scbSetPriority(s8 excpn, u32 priority)
}


u32 _imxrt_scbGetPriority(s8 excpn)
u32 _imxrt_scsExceptionPriorityGet(s8 excpn)
{
volatile u8 *ptr = (u8 *)&scs_common.scs->shpr1 + excpn - 4;

return *ptr >> 4;
}


void _hal_scbSystemReset(void)
void _hal_scsSystemReset(void)
{
scs_common.scs->aircr = ((0x5fau << 16) | (scs_common.scs->aircr & (0x700u)) | (1u << 2));

Expand All @@ -188,13 +188,13 @@ void _hal_scbSystemReset(void)
}


unsigned int _hal_scbCpuid(void)
unsigned int _hal_scsCpuID(void)
{
return scs_common.scs->cpuid;
}


void _hal_scbSetFPU(int state)
void _hal_scsFPUSet(int state)
{
if (state != 0) {
scs_common.scs->cpacr |= 0xf << 20;
Expand All @@ -209,7 +209,7 @@ void _hal_scbSetFPU(int state)

static int _hal_scbCacheIsSupported(void)
{
u32 partno = ((_hal_scbCpuid() >> 4) & 0xfff);
u32 partno = ((_hal_scsCpuID() >> 4) & 0xfff);

/* Only supported on Cortex-M7 for now */
if (partno == 0xc27) {
Expand All @@ -220,7 +220,7 @@ static int _hal_scbCacheIsSupported(void)
}


void _hal_scbEnableDCache(void)
void _hal_scsDCacheEnable(void)
{
u32 ccsidr, sets, ways;

Expand Down Expand Up @@ -252,7 +252,7 @@ void _hal_scbEnableDCache(void)
}


void _hal_scbDisableDCache(void)
void _hal_scsDCacheDisable(void)
{
register u32 ccsidr, sets, ways;

Expand Down Expand Up @@ -281,7 +281,7 @@ void _hal_scbDisableDCache(void)
}


void _hal_scbCleanInvalDCacheAddr(void *addr, u32 sz)
void _hal_scsDCacheCleanInvalAddr(void *addr, u32 sz)
{
u32 daddr;
int dsize;
Expand Down Expand Up @@ -310,7 +310,7 @@ void _hal_scbCleanInvalDCacheAddr(void *addr, u32 sz)
}


void _hal_scbEnableICache(void)
void _hal_scsICacheEnable(void)
{
if (_hal_scbCacheIsSupported() == 0) {
return;
Expand All @@ -329,7 +329,7 @@ void _hal_scbEnableICache(void)
}


void _hal_scbDisableICache(void)
void _hal_scsICacheDisable(void)
{
if (_hal_scbCacheIsSupported() == 0) {
return;
Expand All @@ -344,7 +344,7 @@ void _hal_scbDisableICache(void)
}


void _hal_scbSetDeepSleep(int state)
void _hal_scsDeepSleepSet(int state)
{
if (state != 0) {
scs_common.scs->scr |= 1 << 2;
Expand All @@ -357,7 +357,7 @@ void _hal_scbSetDeepSleep(int state)
}


void _hal_scbSystickInit(u32 load)
void _hal_scsSystickInit(u32 load)
{
scs_common.scs->rvr = load;
scs_common.scs->cvr = 0;
Expand Down
38 changes: 19 additions & 19 deletions hal/arm/scs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -21,61 +21,61 @@
#include "hal/types.h"


void _hal_nvicSetIRQ(s8 irqn, u8 state);
void _hal_scsIRQSet(s8 irqn, u8 state);


void _hal_nvicSetPriority(s8 irqn, u32 priority);
void _hal_scsIRQPrioritySet(s8 irqn, u32 priority);


void _hal_nvicSetPending(s8 irqn);
void _hal_scsIRQPendingSet(s8 irqn);


int _hal_nvicGetPendingIRQ(s8 irqn);
int _hal_scsIRQPendingGet(s8 irqn);


int _hal_nvicGetActive(s8 irqn);
int _hal_scsIRQActiveGet(s8 irqn);


void _hal_scbSetPriorityGrouping(u32 group);
void _hal_scsPriorityGroupingSet(u32 group);


u32 _hal_scbGetPriorityGrouping(void);
u32 _hal_scsPriorityGroupingGet(void);


void _hal_scbSetPriority(s8 excpn, u32 priority);
void _hal_scsExceptionPrioritySet(s8 excpn, u32 priority);


u32 _imxrt_scbGetPriority(s8 excpn);
u32 _imxrt_scsExceptionPriorityGet(s8 excpn);


void _hal_scbSystemReset(void);
void _hal_scsSystemReset(void);


unsigned int _hal_scbCpuid(void);
unsigned int _hal_scsCpuID(void);


void _hal_scbSetFPU(int state);
void _hal_scsFPUSet(int state);


void _hal_scbEnableDCache(void);
void _hal_scsDCacheEnable(void);


void _hal_scbDisableDCache(void);
void _hal_scsDCacheDisable(void);


void _hal_scbCleanInvalDCacheAddr(void *addr, u32 sz);
void _hal_scsDCacheCleanInvalAddr(void *addr, u32 sz);


void _hal_scbEnableICache(void);
void _hal_scsICacheEnable(void);


void _hal_scbDisableICache(void);
void _hal_scsICacheDisable(void);


void _hal_scbSetDeepSleep(int state);
void _hal_scsDeepSleepSet(int state);


void _hal_scbSystickInit(u32 load);
void _hal_scsSystickInit(u32 load);


void _hal_scsInit(void);
Expand Down
6 changes: 3 additions & 3 deletions hal/armv7m/cpu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -195,7 +195,7 @@ void hal_cpuSigreturn(void *kstack, void *ustack, cpu_context_t **ctx)
char *hal_cpuInfo(char *info)
{
int i;
unsigned int cpuinfo = _hal_scbCpuid();
unsigned int cpuinfo = _hal_scsCpuID();

hal_strcpy(info, HAL_NAME_PLATFORM);
i = sizeof(HAL_NAME_PLATFORM) - 1;
Expand Down Expand Up @@ -276,7 +276,7 @@ void hal_wdgReload(void)

void hal_cpuReboot(void)
{
_hal_scbSystemReset();
_hal_scsSystemReset();
}


Expand All @@ -285,7 +285,7 @@ void hal_cpuReboot(void)

void hal_cleanDCache(ptr_t start, size_t len)
{
_hal_scbCleanInvalDCacheAddr((void *)start, len);
_hal_scsDCacheCleanInvalAddr((void *)start, len);
}


Expand Down
18 changes: 9 additions & 9 deletions hal/armv7m/imxrt/10xx/imxrt10xx.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -546,7 +546,7 @@ int hal_platformctl(void *ptr)
case pctl_reboot:
if (data->action == pctl_set) {
if (data->reboot.magic == PCTL_REBOOT_MAGIC) {
_hal_scbSystemReset();
_hal_scsSystemReset();
}
}
else if (data->action == pctl_get) {
Expand All @@ -558,12 +558,12 @@ int hal_platformctl(void *ptr)
case pctl_devcache:
if (data->action == pctl_set) {
if (data->devcache.state == 0) {
_hal_scbDisableDCache();
_hal_scbDisableICache();
_hal_scsDCacheDisable();
_hal_scsICacheDisable();
}
else {
_hal_scbEnableDCache();
_hal_scbEnableICache();
_hal_scsDCacheEnable();
_hal_scsICacheEnable();
}

ret = EOK;
Expand All @@ -572,7 +572,7 @@ int hal_platformctl(void *ptr)

case pctl_cleanInvalDCache:
if (data->action == pctl_set) {
_hal_scbCleanInvalDCacheAddr(data->cleanInvalDCache.addr, data->cleanInvalDCache.sz);
_hal_scsDCacheCleanInvalAddr(data->cleanInvalDCache.addr, data->cleanInvalDCache.sz);
ret = EOK;
}
break;
Expand Down Expand Up @@ -1961,8 +1961,8 @@ void _imxrt_init(void)
}

/* Configure cache */
_hal_scbEnableDCache();
_hal_scbEnableICache();
_hal_scsDCacheEnable();
_hal_scsICacheEnable();

_imxrt_ccmControlGate(pctl_clk_iomuxc, clk_state_run_wait);

Expand Down Expand Up @@ -2018,5 +2018,5 @@ void _imxrt_init(void)
_imxrt_ccmControlGate(GPT_BUS_CLK, clk_state_run_wait);

/* Enable FPU */
_hal_scbSetFPU(1);
_hal_scsFPUSet(1);
}
14 changes: 7 additions & 7 deletions hal/armv7m/imxrt/117x/imxrt117x.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -666,7 +666,7 @@ int hal_platformctl(void *ptr)
case pctl_reboot:
if (data->action == pctl_set) {
if (data->reboot.magic == PCTL_REBOOT_MAGIC) {
_hal_scbSystemReset();
_hal_scsSystemReset();
}
}
else if (data->action == pctl_get) {
Expand All @@ -678,12 +678,12 @@ int hal_platformctl(void *ptr)
case pctl_devcache:
if (data->action == pctl_set) {
if (data->devcache.state == 0) {
_hal_scbDisableDCache();
_hal_scbDisableICache();
_hal_scsDCacheDisable();
_hal_scsICacheDisable();
}
else {
_hal_scbEnableDCache();
_hal_scbEnableICache();
_hal_scsDCacheEnable();
_hal_scsICacheEnable();
}

ret = EOK;
Expand All @@ -692,7 +692,7 @@ int hal_platformctl(void *ptr)

case pctl_cleanInvalDCache:
if (data->action == pctl_set) {
_hal_scbCleanInvalDCacheAddr(data->cleanInvalDCache.addr, data->cleanInvalDCache.sz);
_hal_scsDCacheCleanInvalAddr(data->cleanInvalDCache.addr, data->cleanInvalDCache.sz);
ret = EOK;
}
break;
Expand Down Expand Up @@ -812,5 +812,5 @@ void _imxrt_init(void)
_imxrt_setDevClock(GPT_BUS_CLK, 0, 4, 0, 0, 1);

/* Enable FPU */
_hal_scbSetFPU(1);
_hal_scsFPUSet(1);
}
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