riscv64: boot from PLO #448
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agkaminski
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Jan 26, 2024
| /* interrupts */ | ||
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| static inline void hal_cpuDisableInterrupts(void) | ||
| { | ||
| __asm__ ("csrc sstatus, 2"); | ||
| __asm__ volatile("csrc sstatus, 2"); |
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silly clang-format thinks this is a function
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| __asm__ volatile("csrc sstatus, 2"); | |
| __asm__ volatile ("csrc sstatus, 2"); |
| : "=r" (*(cycles_t *)cb)); | ||
| return; | ||
| /* clang-format off */ | ||
| __asm__ volatile("rdcycle %0" : "=r"(*(cycles_t *)cb)); |
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| __asm__ volatile("rdcycle %0" : "=r"(*(cycles_t *)cb)); | |
| __asm__ volatile ("rdcycle %0" : "=r" (*(cycles_t *)cb)); |
JIRA: RTOS-550
JIRA: RTOS-550
JIRA: RTOS-550
- simplify interrupt handling code - fix timer interval setting - properly handle interrupts from CLINT and PLIC - remove reading from exec-only pages - mapping is now done correctly JIRA: RTOS-550
JIRA: RTOS-550
JIRA: RTOS-550
Modified kstack approach to be the same as on LEON3. Previously kstack wasn't set correctly, resulting in `fork` failure. JIRA: RTOS-550
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Description
hal_cpuKernelStackvariable to storekstackvalue - same approach as onsparcv8leon3. Previouslykstackwas set incorrectly, causing exception afterfork. Variable use here is the most optimal, as when in the future we'll use more cores,tpregister will have to be reserved in kernel.Motivation and Context
Types of changes
How Has This Been Tested?
riscv64-generic-qemuChecklist:
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