wip: Floo macros #444
fischetifloogen.yml
on: push
Matrix: gen-nocs
unit-test
36s
lint-nocs
50s
Annotations
22 warnings
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[verible-verilog-lint] hw/floo_narrow_wide_chimney.sv#L90:
hw/floo_narrow_wide_chimney.sv#L90
Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/floo_narrow_wide_chimney.sv#L91:
hw/floo_narrow_wide_chimney.sv#L91
Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/floo_pkg.sv#L158:
hw/floo_pkg.sv#L158
Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default]
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[verible-verilog-lint] hw/floo_pkg.sv#L168:
hw/floo_pkg.sv#L168
Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default]
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[verible-verilog-lint] hw/floo_pkg.sv#L194:
hw/floo_pkg.sv#L194
Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/floo_pkg.sv#L211:
hw/floo_pkg.sv#L211
Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/floo_rob.sv#L280:
hw/floo_rob.sv#L280
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/floo_rob.sv#L325:
hw/floo_rob.sv#L325
Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/tb/tb_floo_narrow_wide_chimney.sv#L55:
hw/tb/tb_floo_narrow_wide_chimney.sv#L55
Line length exceeds max: 100; is: 131 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/tb/tb_floo_rob.sv#L232:
hw/tb/tb_floo_rob.sv#L232
Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/floo_axi_chimney.sv#L72:
hw/floo_axi_chimney.sv#L72
Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/tb/tb_floo_dma_mesh.sv#L28:
hw/tb/tb_floo_dma_mesh.sv#L28
Line length exceeds max: 100; is: 131 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/tb/tb_floo_dma_mesh.sv#L256:
hw/tb/tb_floo_dma_mesh.sv#L256
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/floo_narrow_wide_router.sv#L11:
hw/floo_narrow_wide_router.sv#L11
Declared module does not match the first dot-delimited component of file name: "floo_narrow_wide_router" [Style: file-names] [module-filename]
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[verible-verilog-lint] hw/floo_narrow_wide_router.sv#L58:
hw/floo_narrow_wide_router.sv#L58
Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/floo_narrow_wide_router.sv#L59:
hw/floo_narrow_wide_router.sv#L59
Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/floo_vc_narrow_wide_chimney.sv#L106:
hw/floo_vc_narrow_wide_chimney.sv#L106
Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/floo_vc_narrow_wide_chimney.sv#L107:
hw/floo_vc_narrow_wide_chimney.sv#L107
Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/tb/tb_floo_vc_dma_mesh.sv#L29:
hw/tb/tb_floo_vc_dma_mesh.sv#L29
Line length exceeds max: 100; is: 131 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/tb/tb_floo_vc_dma_mesh.sv#L284:
hw/tb/tb_floo_vc_dma_mesh.sv#L284
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/floo_vc_narrow_wide_router.sv#L83:
hw/floo_vc_narrow_wide_router.sv#L83
Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/floo_vc_narrow_wide_router.sv#L84:
hw/floo_vc_narrow_wide_router.sv#L84
Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]
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Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
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occamy_mesh
Expired
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11.1 KB |
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occamy_mesh_src
Expired
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17 KB |
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occamy_tree
Expired
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7.45 KB |
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single_cluster
Expired
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2.07 KB |
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terapool
Expired
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11.4 KB |
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verible-linter
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426 Bytes |
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