Node.js 16 actions are deprecated. Please update the following actions to use Node.js 20: actions/checkout@v3. For more information see: https://github.blog/changelog/2023-09-22-github-actions-transitioning-from-node-16-to-node-20/.

Node.js 16 actions are deprecated. Please update the following actions to use Node.js 20: actions/checkout@v3, actions/setup-python@v2. For more information see: https://github.blog/changelog/2023-09-22-github-actions-transitioning-from-node-16-to-node-20/.

The following actions uses node12 which is deprecated and will be forced to run on node16: actions/setup-python@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/floo_mesh_ruche.sv:63:- flit_t [RucheWest:RucheNorth][NumPhysChannels-1:0] ruche_in_flit; hw/floo_mesh_ruche.sv:64:- logic [RucheWest:RucheNorth][NumVirtChannels-1:0] ruche_in_ready, ruche_in_valid; hw/floo_mesh_ruche.sv:65:- flit_t [RucheWest:RucheNorth][NumPhysChannels-1:0] ruche_out_flit; hw/floo_mesh_ruche.sv:66:- logic [RucheWest:RucheNorth][NumVirtChannels-1:0] ruche_out_ready, ruche_out_valid; hw/floo_mesh_ruche.sv:63:+ flit_t [RucheWest:RucheNorth][NumPhysChannels-1:0] ruche_in_flit; hw/floo_mesh_ruche.sv:64:+ logic [RucheWest:RucheNorth][NumVirtChannels-1:0] ruche_in_ready, ruche_in_valid; hw/floo_mesh_ruche.sv:65:+ flit_t [RucheWest:RucheNorth][NumPhysChannels-1:0] ruche_out_flit; hw/floo_mesh_ruche.sv:66:+ logic [RucheWest:RucheNorth][NumVirtChannels-1:0] ruche_out_ready, ruche_out_valid;

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/floo_route_select.sv:9:-module floo_route_select import floo_pkg::*; hw/floo_route_select.sv:10:- #( hw/floo_route_select.sv:11:- parameter int unsigned NumRoutes = 0, hw/floo_route_select.sv:12:- parameter type flit_t = logic, hw/floo_route_select.sv:13:- parameter route_algo_e RouteAlgo = IdTable, hw/floo_route_select.sv:14:- parameter bit LockRouting = 1'b1, hw/floo_route_select.sv:15:- /// Used for ID-based and XY routing hw/floo_route_select.sv:16:- parameter int unsigned IdWidth = 0, hw/floo_route_select.sv:17:- /// Used for ID-based routing hw/floo_route_select.sv:18:- parameter int unsigned NumAddrRules = 0, hw/floo_route_select.sv:19:- parameter type addr_rule_t = logic, hw/floo_route_select.sv:20:- parameter type id_t = logic[IdWidth-1:0], hw/floo_route_select.sv:21:- /// Used for source-based routing hw/floo_route_select.sv:22:- parameter int unsigned RouteSelWidth = $clog2(NumRoutes) hw/floo_route_select.sv:9:+module floo_route_select hw/floo_route_select.sv:10:+ import floo_pkg::*; hw/floo_route_select.sv:11:+#( hw/floo_route_select.sv:12:+ parameter int unsigned NumRoutes = 0, hw/floo_route_select.sv:13:+ parameter type flit_t = logic, hw/floo_route_select.sv:14:+ parameter route_algo_e RouteAlgo = IdTable, hw/floo_route_select.sv:15:+ parameter bit LockRouting = 1'b1, hw/floo_route_select.sv:16:+ /// Used for ID-based and XY routing hw/floo_route_select.sv:17:+ parameter int unsigned IdWidth = 0, hw/floo_route_select.sv:18:+ /// Used for ID-based routing hw/floo_route_select.sv:19:+ parameter int unsigned NumAddrRules = 0, hw/floo_route_select.sv:20:+ parameter type addr_rule_t = logic, hw/floo_route_select.sv:21:+ parameter type id_t = logic [IdWidth-1:0], hw/floo_route_select.sv:22:+ /// Used for source-based routing hw/floo_route_select.sv:23:+ parameter int unsigned RouteSelWidth = $clog2(NumRoutes)

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/floo_route_select.sv:24:- input logic clk_i, hw/floo_route_select.sv:25:- input logic rst_ni, hw/floo_route_select.sv:26:- input logic test_enable_i, hw/floo_route_select.sv:27:- hw/floo_route_select.sv:28:- input id_t xy_id_i, hw/floo_route_select.sv:29:- input addr_rule_t [NumAddrRules-1:0] id_route_map_i, hw/floo_route_select.sv:30:- hw/floo_route_select.sv:31:- input flit_t channel_i, hw/floo_route_select.sv:32:- input logic valid_i, hw/floo_route_select.sv:33:- input logic ready_i, hw/floo_route_select.sv:34:- output flit_t channel_o, hw/floo_route_select.sv:35:- output logic [ NumRoutes-1:0] route_sel_o, // One-hot route hw/floo_route_select.sv:36:- output logic [RouteSelWidth-1:0]route_sel_id_o hw/floo_route_select.sv:25:+ input logic clk_i, hw/floo_route_select.sv:26:+ input logic rst_ni, hw/floo_route_select.sv:27:+ input logic test_enable_i, hw/floo_route_select.sv:28:+ hw/floo_route_select.sv:29:+ input id_t xy_id_i, hw/floo_route_select.sv:30:+ input addr_rule_t [NumAddrRules-1:0] id_route_map_i, hw/floo_route_select.sv:31:+ hw/floo_route_select.sv:32:+ input flit_t channel_i, hw/floo_route_select.sv:33:+ input logic valid_i, hw/floo_route_select.sv:34:+ input logic ready_i, hw/floo_route_select.sv:35:+ output flit_t channel_o, hw/floo_route_select.sv:36:+ output logic [ NumRoutes-1:0] route_sel_o, // One-hot route hw/floo_route_select.sv:37:+ output logic [RouteSelWidth-1:0] route_sel_id_o

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/floo_route_select.sv:68:- .addr_i ( channel_i.hdr.dst_id ), hw/floo_route_select.sv:69:- .addr_map_i ( id_route_map_i ), hw/floo_route_select.sv:70:- .idx_o ( id_table_result ), hw/floo_route_select.sv:71:- .dec_valid_o (), hw/floo_route_select.sv:72:- .dec_error_o (), hw/floo_route_select.sv:73:- .default_idx_i ('0), hw/floo_route_select.sv:74:- .en_default_idx_i ('0) hw/floo_route_select.sv:69:+ .addr_i (channel_i.hdr.dst_id), hw/floo_route_select.sv:70:+ .addr_map_i (id_route_map_i), hw/floo_route_select.sv:71:+ .idx_o (id_table_result), hw/floo_route_select.sv:72:+ .dec_valid_o (), hw/floo_route_select.sv:73:+ .dec_error_o (), hw/floo_route_select.sv:74:+ .default_idx_i ('0), hw/floo_route_select.sv:75:+ .en_default_idx_i('0)

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/floo_router.sv:93:- .clk_i, hw/floo_router.sv:94:- .rst_ni, hw/floo_router.sv:95:- .test_enable_i, hw/floo_router.sv:96:- hw/floo_router.sv:97:- .xy_id_i ( xy_id_i ), hw/floo_router.sv:98:- .id_route_map_i ( id_route_map_i ), hw/floo_router.sv:99:- .channel_i ( in_data [in_route][v_chan] ), hw/floo_router.sv:100:- .valid_i ( in_valid [in_route][v_chan] ), hw/floo_router.sv:101:- .ready_i ( in_ready [in_route][v_chan] ), hw/floo_router.sv:102:- .channel_o ( in_routed_data[in_route][v_chan] ), hw/floo_router.sv:103:- .route_sel_o ( route_mask [in_route][v_chan] ), hw/floo_router.sv:104:- .route_sel_id_o ( ) hw/floo_router.sv:95:+ .clk_i, hw/floo_router.sv:96:+ .rst_ni, hw/floo_router.sv:97:+ .test_enable_i, hw/floo_router.sv:98:+ hw/floo_router.sv:99:+ .xy_id_i (xy_id_i), hw/floo_router.sv:100:+ .id_route_map_i(id_route_map_i), hw/floo_router.sv:101:+ .channel_i (in_data[in_route][v_chan]), hw/floo_router.sv:102:+ .valid_i (in_valid[in_route][v_chan]), hw/floo_router.sv:103:+ .ready_i (in_ready[in_route][v_chan]), hw/floo_router.sv:104:+ .channel_o (in_routed_data[in_route][v_chan]), hw/floo_router.sv:105:+ .route_sel_o (route_mask[in_route][v_chan]), hw/floo_router.sv:106:+ .route_sel_id_o()

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/tb/tb_floo_dma_mesh.sv:167:- assign req_ver_neg[NumY] = req_hbm_out; hw/tb/tb_floo_dma_mesh.sv:168:- assign rsp_ver_neg[NumY] = rsp_hbm_out; hw/tb/tb_floo_dma_mesh.sv:169:- assign wide_ver_neg[NumY] = wide_hbm_out; hw/tb/tb_floo_dma_mesh.sv:170:- end hw/tb/tb_floo_dma_mesh.sv:171:- else if (i == South) begin : gen_south_hbm_chimneys hw/tb/tb_floo_dma_mesh.sv:167:+ assign req_ver_neg[NumY] = req_hbm_out; hw/tb/tb_floo_dma_mesh.sv:168:+ assign rsp_ver_neg[NumY] = rsp_hbm_out; hw/tb/tb_floo_dma_mesh.sv:169:+ assign wide_ver_neg[NumY] = wide_hbm_out; hw/tb/tb_floo_dma_mesh.sv:170:+ end else if (i == South) begin : gen_south_hbm_chimneys

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/tb/tb_floo_dma_mesh.sv:175:- assign req_hbm_in = req_ver_neg[0]; hw/tb/tb_floo_dma_mesh.sv:176:- assign rsp_hbm_in = rsp_ver_neg[0]; hw/tb/tb_floo_dma_mesh.sv:177:- assign wide_hbm_in = wide_ver_neg[0]; hw/tb/tb_floo_dma_mesh.sv:178:- assign req_ver_pos[0] = req_hbm_out; hw/tb/tb_floo_dma_mesh.sv:179:- assign rsp_ver_pos[0] = rsp_hbm_out; hw/tb/tb_floo_dma_mesh.sv:180:- assign wide_ver_pos[0] = wide_hbm_out; hw/tb/tb_floo_dma_mesh.sv:181:- end hw/tb/tb_floo_dma_mesh.sv:182:- else if (i == East) begin : gen_east_hbm_chimneys hw/tb/tb_floo_dma_mesh.sv:174:+ assign req_hbm_in = req_ver_neg[0]; hw/tb/tb_floo_dma_mesh.sv:175:+ assign rsp_hbm_in = rsp_ver_neg[0]; hw/tb/tb_floo_dma_mesh.sv:176:+ assign wide_hbm_in = wide_ver_neg[0]; hw/tb/tb_floo_dma_mesh.sv:177:+ assign req_ver_pos[0] = req_hbm_out; hw/tb/tb_floo_dma_mesh.sv:178:+ assign rsp_ver_pos[0] = rsp_hbm_out; hw/tb/tb_floo_dma_mesh.sv:179:+ assign wide_ver_pos[0] = wide_hbm_out; hw/tb/tb_floo_dma_mesh.sv:180:+ end else if (i == East) begin : gen_east_hbm_chimneys

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/tb/tb_floo_dma_mesh.sv:189:- assign req_hor_neg[NumX] = req_hbm_out; hw/tb/tb_floo_dma_mesh.sv:190:- assign rsp_hor_neg[NumX] = rsp_hbm_out; hw/tb/tb_floo_dma_mesh.sv:191:- assign wide_hor_neg[NumX] = wide_hbm_out; hw/tb/tb_floo_dma_mesh.sv:192:- end hw/tb/tb_floo_dma_mesh.sv:193:- else if (i == West) begin : gen_west_hbm_chimneys hw/tb/tb_floo_dma_mesh.sv:187:+ assign req_hor_neg[NumX] = req_hbm_out; hw/tb/tb_floo_dma_mesh.sv:188:+ assign rsp_hor_neg[NumX] = rsp_hbm_out; hw/tb/tb_floo_dma_mesh.sv:189:+ assign wide_hor_neg[NumX] = wide_hbm_out; hw/tb/tb_floo_dma_mesh.sv:190:+ end else if (i == West) begin : gen_west_hbm_chimneys

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/tb/tb_floo_dma_mesh.sv:197:- assign req_hbm_in = req_hor_neg[0]; hw/tb/tb_floo_dma_mesh.sv:198:- assign rsp_hbm_in = rsp_hor_neg[0]; hw/tb/tb_floo_dma_mesh.sv:199:- assign wide_hbm_in = wide_hor_neg[0]; hw/tb/tb_floo_dma_mesh.sv:200:- assign req_hor_pos[0] = req_hbm_out; hw/tb/tb_floo_dma_mesh.sv:201:- assign rsp_hor_pos[0] = rsp_hbm_out; hw/tb/tb_floo_dma_mesh.sv:202:- assign wide_hor_pos[0] = wide_hbm_out; hw/tb/tb_floo_dma_mesh.sv:194:+ assign req_hbm_in = req_hor_neg[0]; hw/tb/tb_floo_dma_mesh.sv:195:+ assign rsp_hbm_in = rsp_hor_neg[0]; hw/tb/tb_floo_dma_mesh.sv:196:+ assign wide_hbm_in = wide_hor_neg[0]; hw/tb/tb_floo_dma_mesh.sv:197:+ assign req_hor_pos[0] = req_hbm_out; hw/tb/tb_floo_dma_mesh.sv:198:+ assign rsp_hor_pos[0] = rsp_hbm_out; hw/tb/tb_floo_dma_mesh.sv:199:+ assign wide_hor_pos[0] = wide_hbm_out;

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/tb/tb_floo_dma_mesh.sv:257:- .TA ( ApplTime ), hw/tb/tb_floo_dma_mesh.sv:258:- .TT ( TestTime ), hw/tb/tb_floo_dma_mesh.sv:259:- .DataWidth ( AxiNarrowInDataWidth ), hw/tb/tb_floo_dma_mesh.sv:260:- .AddrWidth ( AxiNarrowInAddrWidth ), hw/tb/tb_floo_dma_mesh.sv:261:- .UserWidth ( AxiNarrowInUserWidth ), hw/tb/tb_floo_dma_mesh.sv:262:- .AxiIdInWidth ( AxiNarrowOutIdWidth ), hw/tb/tb_floo_dma_mesh.sv:263:- .AxiIdOutWidth ( AxiNarrowInIdWidth ), hw/tb/tb_floo_dma_mesh.sv:264:- .MemBaseAddr ( MemBaseAddr ), hw/tb/tb_floo_dma_mesh.sv:265:- .MemSize ( MemSize ), hw/tb/tb_floo_dma_mesh.sv:266:- .NumAxInFlight ( 2*NarrowMaxTxnsPerId ), hw/tb/tb_floo_dma_mesh.sv:267:- .axi_in_req_t ( axi_narrow_out_req_t ), hw/tb/tb_floo_dma_mesh.sv:268:- .axi_in_rsp_t ( axi_narrow_out_rsp_t ), hw/tb/tb_floo_dma_mesh.sv:269:- .axi_out_req_t ( axi_narrow_in_req_t ), hw/tb/tb_floo_dma_mesh.sv:270:- .axi_out_rsp_t ( axi_narrow_in_rsp_t ), hw/tb/tb_floo_dma_mesh.sv:271:- .JobId ( 100 + Index ) hw/tb/tb_floo_dma_mesh.sv:254:+ .TA (ApplTime), hw/tb/tb_floo_dma_mesh.sv:255:+ .TT (TestTime), hw/tb/tb_floo_dma_mesh.sv:256:+ .DataWidth (AxiNarrowInDataWidth), hw/tb/tb_floo_dma_mesh.sv:257:+ .AddrWidth (AxiNarrowInAddrWidth), hw/tb/tb_floo_dma_mesh.sv:258:+ .UserWidth (AxiNarrowInUserWidth), hw/tb/tb_floo_dma_mesh.sv:259:+ .AxiIdInWidth (AxiNarrowOutIdWidth), hw/tb/tb_floo_dma_mesh.sv:260:+ .AxiIdOutWidth(AxiNarrowInIdWidth), hw/tb/tb_floo_dma_mesh.sv:261:+ .MemBaseAddr (MemBaseAddr), hw/tb/tb_floo_dma_mesh.sv:262:+ .MemSize (MemSize), hw/tb/tb_floo_dma_mesh.sv:263:+ .NumAxInFlight(2 * NarrowMaxTxnsPerId), hw/tb/tb_floo_dma_mesh.sv:264:+ .axi_in_req_t (axi_narrow_out_req_t), hw/tb/tb_floo_dma_mesh.sv:265:+ .axi_in_rsp_t (axi_narrow_out_rsp_t), hw/tb/tb_floo_dma_mesh.sv:266:+ .axi_out_req_t(axi_narrow_in_req_t), hw/tb/tb_floo_dma_mesh.sv:267:+ .axi_out_rsp_t(axi_narrow_in_rsp_t), hw/tb/tb_floo_dma_mesh.sv:268:+ .JobId (100 + Index)

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/floo_mesh_ruche.sv:63:- flit_t [RucheWest:RucheNorth][NumPhysChannels-1:0] ruche_in_flit; hw/floo_mesh_ruche.sv:64:- logic [RucheWest:RucheNorth][NumVirtChannels-1:0] ruche_in_ready, ruche_in_valid; hw/floo_mesh_ruche.sv:65:- flit_t [RucheWest:RucheNorth][NumPhysChannels-1:0] ruche_out_flit; hw/floo_mesh_ruche.sv:66:- logic [RucheWest:RucheNorth][NumVirtChannels-1:0] ruche_out_ready, ruche_out_valid; hw/floo_mesh_ruche.sv:63:+ flit_t [RucheWest:RucheNorth][NumPhysChannels-1:0] ruche_in_flit; hw/floo_mesh_ruche.sv:64:+ logic [RucheWest:RucheNorth][NumVirtChannels-1:0] ruche_in_ready, ruche_in_valid; hw/floo_mesh_ruche.sv:65:+ flit_t [RucheWest:RucheNorth][NumPhysChannels-1:0] ruche_out_flit; hw/floo_mesh_ruche.sv:66:+ logic [RucheWest:RucheNorth][NumVirtChannels-1:0] ruche_out_ready, ruche_out_valid;

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/floo_route_select.sv:9:-module floo_route_select import floo_pkg::*; hw/floo_route_select.sv:10:- #( hw/floo_route_select.sv:11:- parameter int unsigned NumRoutes = 0, hw/floo_route_select.sv:12:- parameter type flit_t = logic, hw/floo_route_select.sv:13:- parameter route_algo_e RouteAlgo = IdTable, hw/floo_route_select.sv:14:- parameter bit LockRouting = 1'b1, hw/floo_route_select.sv:15:- /// Used for ID-based and XY routing hw/floo_route_select.sv:16:- parameter int unsigned IdWidth = 0, hw/floo_route_select.sv:17:- /// Used for ID-based routing hw/floo_route_select.sv:18:- parameter int unsigned NumAddrRules = 0, hw/floo_route_select.sv:19:- parameter type addr_rule_t = logic, hw/floo_route_select.sv:20:- parameter type id_t = logic[IdWidth-1:0], hw/floo_route_select.sv:21:- /// Used for source-based routing hw/floo_route_select.sv:22:- parameter int unsigned RouteSelWidth = $clog2(NumRoutes) hw/floo_route_select.sv:9:+module floo_route_select hw/floo_route_select.sv:10:+ import floo_pkg::*; hw/floo_route_select.sv:11:+#( hw/floo_route_select.sv:12:+ parameter int unsigned NumRoutes = 0, hw/floo_route_select.sv:13:+ parameter type flit_t = logic, hw/floo_route_select.sv:14:+ parameter route_algo_e RouteAlgo = IdTable, hw/floo_route_select.sv:15:+ parameter bit LockRouting = 1'b1, hw/floo_route_select.sv:16:+ /// Used for ID-based and XY routing hw/floo_route_select.sv:17:+ parameter int unsigned IdWidth = 0, hw/floo_route_select.sv:18:+ /// Used for ID-based routing hw/floo_route_select.sv:19:+ parameter int unsigned NumAddrRules = 0, hw/floo_route_select.sv:20:+ parameter type addr_rule_t = logic, hw/floo_route_select.sv:21:+ parameter type id_t = logic [IdWidth-1:0], hw/floo_route_select.sv:22:+ /// Used for source-based routing hw/floo_route_select.sv:23:+ parameter int unsigned RouteSelWidth = $clog2(NumRoutes)

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/floo_route_select.sv:24:- input logic clk_i, hw/floo_route_select.sv:25:- input logic rst_ni, hw/floo_route_select.sv:26:- input logic test_enable_i, hw/floo_route_select.sv:27:- hw/floo_route_select.sv:28:- input id_t xy_id_i, hw/floo_route_select.sv:29:- input addr_rule_t [NumAddrRules-1:0] id_route_map_i, hw/floo_route_select.sv:30:- hw/floo_route_select.sv:31:- input flit_t channel_i, hw/floo_route_select.sv:32:- input logic valid_i, hw/floo_route_select.sv:33:- input logic ready_i, hw/floo_route_select.sv:34:- output flit_t channel_o, hw/floo_route_select.sv:35:- output logic [ NumRoutes-1:0] route_sel_o, // One-hot route hw/floo_route_select.sv:36:- output logic [RouteSelWidth-1:0]route_sel_id_o hw/floo_route_select.sv:25:+ input logic clk_i, hw/floo_route_select.sv:26:+ input logic rst_ni, hw/floo_route_select.sv:27:+ input logic test_enable_i, hw/floo_route_select.sv:28:+ hw/floo_route_select.sv:29:+ input id_t xy_id_i, hw/floo_route_select.sv:30:+ input addr_rule_t [NumAddrRules-1:0] id_route_map_i, hw/floo_route_select.sv:31:+ hw/floo_route_select.sv:32:+ input flit_t channel_i, hw/floo_route_select.sv:33:+ input logic valid_i, hw/floo_route_select.sv:34:+ input logic ready_i, hw/floo_route_select.sv:35:+ output flit_t channel_o, hw/floo_route_select.sv:36:+ output logic [ NumRoutes-1:0] route_sel_o, // One-hot route hw/floo_route_select.sv:37:+ output logic [RouteSelWidth-1:0] route_sel_id_o

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/floo_route_select.sv:68:- .addr_i ( channel_i.hdr.dst_id ), hw/floo_route_select.sv:69:- .addr_map_i ( id_route_map_i ), hw/floo_route_select.sv:70:- .idx_o ( id_table_result ), hw/floo_route_select.sv:71:- .dec_valid_o (), hw/floo_route_select.sv:72:- .dec_error_o (), hw/floo_route_select.sv:73:- .default_idx_i ('0), hw/floo_route_select.sv:74:- .en_default_idx_i ('0) hw/floo_route_select.sv:69:+ .addr_i (channel_i.hdr.dst_id), hw/floo_route_select.sv:70:+ .addr_map_i (id_route_map_i), hw/floo_route_select.sv:71:+ .idx_o (id_table_result), hw/floo_route_select.sv:72:+ .dec_valid_o (), hw/floo_route_select.sv:73:+ .dec_error_o (), hw/floo_route_select.sv:74:+ .default_idx_i ('0), hw/floo_route_select.sv:75:+ .en_default_idx_i('0)

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/floo_router.sv:93:- .clk_i, hw/floo_router.sv:94:- .rst_ni, hw/floo_router.sv:95:- .test_enable_i, hw/floo_router.sv:96:- hw/floo_router.sv:97:- .xy_id_i ( xy_id_i ), hw/floo_router.sv:98:- .id_route_map_i ( id_route_map_i ), hw/floo_router.sv:99:- .channel_i ( in_data [in_route][v_chan] ), hw/floo_router.sv:100:- .valid_i ( in_valid [in_route][v_chan] ), hw/floo_router.sv:101:- .ready_i ( in_ready [in_route][v_chan] ), hw/floo_router.sv:102:- .channel_o ( in_routed_data[in_route][v_chan] ), hw/floo_router.sv:103:- .route_sel_o ( route_mask [in_route][v_chan] ), hw/floo_router.sv:104:- .route_sel_id_o ( ) hw/floo_router.sv:95:+ .clk_i, hw/floo_router.sv:96:+ .rst_ni, hw/floo_router.sv:97:+ .test_enable_i, hw/floo_router.sv:98:+ hw/floo_router.sv:99:+ .xy_id_i (xy_id_i), hw/floo_router.sv:100:+ .id_route_map_i(id_route_map_i), hw/floo_router.sv:101:+ .channel_i (in_data[in_route][v_chan]), hw/floo_router.sv:102:+ .valid_i (in_valid[in_route][v_chan]), hw/floo_router.sv:103:+ .ready_i (in_ready[in_route][v_chan]), hw/floo_router.sv:104:+ .channel_o (in_routed_data[in_route][v_chan]), hw/floo_router.sv:105:+ .route_sel_o (route_mask[in_route][v_chan]), hw/floo_router.sv:106:+ .route_sel_id_o()

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/tb/tb_floo_dma_mesh.sv:167:- assign req_ver_neg[NumY] = req_hbm_out; hw/tb/tb_floo_dma_mesh.sv:168:- assign rsp_ver_neg[NumY] = rsp_hbm_out; hw/tb/tb_floo_dma_mesh.sv:169:- assign wide_ver_neg[NumY] = wide_hbm_out; hw/tb/tb_floo_dma_mesh.sv:170:- end hw/tb/tb_floo_dma_mesh.sv:171:- else if (i == South) begin : gen_south_hbm_chimneys hw/tb/tb_floo_dma_mesh.sv:167:+ assign req_ver_neg[NumY] = req_hbm_out; hw/tb/tb_floo_dma_mesh.sv:168:+ assign rsp_ver_neg[NumY] = rsp_hbm_out; hw/tb/tb_floo_dma_mesh.sv:169:+ assign wide_ver_neg[NumY] = wide_hbm_out; hw/tb/tb_floo_dma_mesh.sv:170:+ end else if (i == South) begin : gen_south_hbm_chimneys

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/tb/tb_floo_dma_mesh.sv:175:- assign req_hbm_in = req_ver_neg[0]; hw/tb/tb_floo_dma_mesh.sv:176:- assign rsp_hbm_in = rsp_ver_neg[0]; hw/tb/tb_floo_dma_mesh.sv:177:- assign wide_hbm_in = wide_ver_neg[0]; hw/tb/tb_floo_dma_mesh.sv:178:- assign req_ver_pos[0] = req_hbm_out; hw/tb/tb_floo_dma_mesh.sv:179:- assign rsp_ver_pos[0] = rsp_hbm_out; hw/tb/tb_floo_dma_mesh.sv:180:- assign wide_ver_pos[0] = wide_hbm_out; hw/tb/tb_floo_dma_mesh.sv:181:- end hw/tb/tb_floo_dma_mesh.sv:182:- else if (i == East) begin : gen_east_hbm_chimneys hw/tb/tb_floo_dma_mesh.sv:174:+ assign req_hbm_in = req_ver_neg[0]; hw/tb/tb_floo_dma_mesh.sv:175:+ assign rsp_hbm_in = rsp_ver_neg[0]; hw/tb/tb_floo_dma_mesh.sv:176:+ assign wide_hbm_in = wide_ver_neg[0]; hw/tb/tb_floo_dma_mesh.sv:177:+ assign req_ver_pos[0] = req_hbm_out; hw/tb/tb_floo_dma_mesh.sv:178:+ assign rsp_ver_pos[0] = rsp_hbm_out; hw/tb/tb_floo_dma_mesh.sv:179:+ assign wide_ver_pos[0] = wide_hbm_out; hw/tb/tb_floo_dma_mesh.sv:180:+ end else if (i == East) begin : gen_east_hbm_chimneys

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/tb/tb_floo_dma_mesh.sv:189:- assign req_hor_neg[NumX] = req_hbm_out; hw/tb/tb_floo_dma_mesh.sv:190:- assign rsp_hor_neg[NumX] = rsp_hbm_out; hw/tb/tb_floo_dma_mesh.sv:191:- assign wide_hor_neg[NumX] = wide_hbm_out; hw/tb/tb_floo_dma_mesh.sv:192:- end hw/tb/tb_floo_dma_mesh.sv:193:- else if (i == West) begin : gen_west_hbm_chimneys hw/tb/tb_floo_dma_mesh.sv:187:+ assign req_hor_neg[NumX] = req_hbm_out; hw/tb/tb_floo_dma_mesh.sv:188:+ assign rsp_hor_neg[NumX] = rsp_hbm_out; hw/tb/tb_floo_dma_mesh.sv:189:+ assign wide_hor_neg[NumX] = wide_hbm_out; hw/tb/tb_floo_dma_mesh.sv:190:+ end else if (i == West) begin : gen_west_hbm_chimneys

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: hw/tb/tb_floo_dma_mesh.sv:197:- assign req_hbm_in = req_hor_neg[0]; hw/tb/tb_floo_dma_mesh.sv:198:- assign rsp_hbm_in = rsp_hor_neg[0]; hw/tb/tb_floo_dma_mesh.sv:199:- assign wide_hbm_in = wide_hor_neg[0]; hw/tb/tb_floo_dma_mesh.sv:200:- assign req_hor_pos[0] = req_hbm_out; hw/tb/tb_floo_dma_mesh.sv:201:- assign rsp_hor_pos[0] = rsp_hbm_out; hw/tb/tb_floo_dma_mesh.sv:202:- assign wide_hor_pos[0] = wide_hbm_out; hw/tb/tb_floo_dma_mesh.sv:194:+ assign req_hbm_in = req_hor_neg[0]; hw/tb/tb_floo_dma_mesh.sv:195:+ assign rsp_hbm_in = rsp_hor_neg[0]; hw/tb/tb_floo_dma_mesh.sv:196:+ assign wide_hbm_in = wide_hor_neg[0]; hw/tb/tb_floo_dma_mesh.sv:197:+ assign req_hor_pos[0] = req_hbm_out; hw/tb/tb_floo_dma_mesh.sv:198:+ assign rsp_hor_pos[0] = rsp_hbm_out; hw/tb/tb_floo_dma_mesh.sv:199:+ assign wide_hor_pos[0] = wide_hbm_out;