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hw(chimney): Use generate loop over route_comp modules instead of m…
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…odule arrays
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@fischeti
fischeti committed Sep 25, 2024
1 parent f66de94 commit 0e7b060
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101 changes: 62 additions & 39 deletions hw/floo_axi_chimney.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -374,49 +374,72 @@ module floo_axi_chimney #(
// ROUTING //
/////////////////

floo_route_comp #(
.RouteCfg ( RouteCfg ),
.id_t ( id_t ),
.addr_t ( axi_addr_t ),
.addr_rule_t ( sam_rule_t ),
.route_t ( route_t )
) i_floo_req_route_comp [1:0] (
.clk_i,
.rst_ni,
.route_table_i,
.addr_map_i ( Sam ),
.id_i ( id_t'('0) ),
.addr_i ( {axi_aw_queue.addr, axi_ar_queue.addr} ),
.route_o ( {route_out[AxiAw], route_out[AxiAr]} ),
.id_o ( {id_out[AxiAw], id_out[AxiAr]} )
);
if (RouteCfg.RouteAlgo == SourceRouting) begin : gen_route_field
floo_route_comp #(
.RouteCfg ( RouteCfg ),
.UseIdTable ( 1'b0 ), // Overwrite RouteCfg
.id_t ( id_t ),
.addr_t ( axi_addr_t ),
.addr_rule_t ( sam_rule_t ),
.route_t ( route_t )
) i_floo_rsp_route_comp [1:0] (
.clk_i,
.rst_ni,
.route_table_i,
.addr_i ( '0 ),
.addr_map_i ( '0 ),
.id_i ({aw_out_hdr_out.hdr.src_id, ar_out_hdr_out.hdr.src_id} ),
.route_o ({route_out[AxiB], route_out[AxiR]} ),
.id_o ({id_out[AxiB], id_out[AxiR]} )
);
axi_addr_t [NumAxiChannels-1:0] axi_req_addr;
id_t [NumAxiChannels-1:0] axi_rsp_src_id;

assign axi_req_addr[AxiAw] = axi_aw_queue.addr;
assign axi_req_addr[AxiAr] = axi_ar_queue.addr;

assign axi_rsp_src_id[AxiB] = aw_out_hdr_out.hdr.src_id;
assign axi_rsp_src_id[AxiR] = ar_out_hdr_out.hdr.src_id;

for (genvar ch = 0; ch < NumAxiChannels; ch++) begin : gen_route_comp
localparam axi_ch_e axi_ch = axi_ch_e'(ch);

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[verible-verilog-lint] hw/floo_axi_chimney.sv#L387 

Localparam name does not match the naming convention defined by regex pattern: (([A-Z0-9]+[a-z0-9]*)+(_[0-9]+)?) [Style: constants] [parameter-name-style]
Raw output 
message:"Localparam name does not match the naming convention defined by regex pattern: (([A-Z0-9]+[a-z0-9]*)+(_[0-9]+)?) [Style: constants] [parameter-name-style]" location:{path:"./hw/floo_axi_chimney.sv" range:{start:{line:387 column:25}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
if (axi_ch == AxiAw || axi_ch == AxiAr) begin : gen_req_route_comp
// Translate the address from AXI requests to a destination ID
// (or route if `SourceRouting` is used)
floo_route_comp #(
.RouteCfg ( RouteCfg ),
.id_t ( id_t ),
.addr_t ( axi_addr_t ),
.addr_rule_t ( sam_rule_t ),
.route_t ( route_t )
) i_floo_req_route_comp (
.clk_i,
.rst_ni,
.route_table_i,
.addr_map_i ( Sam ),
.id_i ( id_t'('0) ),
.addr_i ( axi_req_addr[ch] ),
.route_o ( route_out[ch] ),
.id_o ( id_out[ch] )
);
end else if (RouteCfg.RouteAlgo == floo_pkg::SourceRouting &&
(axi_ch == AxiB || axi_ch == AxiR)) begin : gen_rsp_route_comp
// Generally, the source ID from the request is used to route back
// the responses. However, in the case of `SourceRouting`, the source ID
// first needs to be translated into a route.
floo_route_comp #(
.RouteCfg ( RouteCfg ),
.UseIdTable ( 1'b0 ), // Overwrite `RouteCfg`
.id_t ( id_t ),
.addr_t ( axi_addr_t ),
.addr_rule_t ( sam_rule_t ),
.route_t ( route_t )
) i_floo_rsp_route_comp (
.clk_i,
.rst_ni,
.route_table_i,
.addr_i ( '0 ),
.addr_map_i ( '0 ),
.id_i ( axi_rsp_src_id[ch] ),
.route_o ( route_out[ch] ),
.id_o ( id_out[ch] )
);
end
end

if (RouteCfg.RouteAlgo == floo_pkg::SourceRouting) begin : gen_route_field
assign route_out[AxiW] = axi_aw_id_q;
assign dst_id = route_out;
end else begin : gen_dst_field
assign dst_id[AxiAw] = id_out[AxiAw];
assign dst_id[AxiAr] = id_out[AxiAr];
assign dst_id[AxiB] = aw_out_hdr_out.hdr.src_id;
assign dst_id[AxiR] = ar_out_hdr_out.hdr.src_id;
assign dst_id[AxiW] = axi_aw_id_q;
assign dst_id[AxiAw] = id_out[AxiAw];
assign dst_id[AxiAr] = id_out[AxiAr];
assign dst_id[AxiB] = aw_out_hdr_out.hdr.src_id;
assign dst_id[AxiR] = ar_out_hdr_out.hdr.src_id;
assign dst_id[AxiW] = axi_aw_id_q;
end

`FFL(axi_aw_id_q, dst_id[AxiAw], axi_aw_queue_valid_out &&
axi_aw_queue_ready_in, '0)

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100 changes: 61 additions & 39 deletions hw/floo_nw_chimney.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -631,47 +631,69 @@ module floo_nw_chimney #(
// ROUTING //
/////////////////

floo_route_comp #(
.RouteCfg ( RouteCfg ),
.id_t ( id_t ),
.addr_t ( axi_addr_t ),
.addr_rule_t ( sam_rule_t ),
.route_t ( route_t )
) i_floo_req_route_comp [3:0] (
.clk_i,
.rst_ni,
.route_table_i,
.addr_map_i ( Sam ),
.id_i ( id_t'('0) ),
.addr_i ({
axi_narrow_aw_queue.addr, axi_narrow_ar_queue.addr,
axi_wide_aw_queue.addr, axi_wide_ar_queue.addr
}),
.route_o ({route_out[NarrowAw], route_out[NarrowAr], route_out[WideAw], route_out[WideAr]} ),
.id_o ({id_out[NarrowAw], id_out[NarrowAr],id_out[WideAw], id_out[WideAr]} )
);
axi_addr_t [NumNWAxiChannels-1:0] axi_req_addr;
id_t [NumNWAxiChannels-1:0] axi_rsp_src_id;

assign axi_req_addr[NarrowAw] = axi_narrow_aw_queue.addr;
assign axi_req_addr[NarrowAr] = axi_narrow_ar_queue.addr;
assign axi_req_addr[WideAw] = axi_wide_aw_queue.addr;
assign axi_req_addr[WideAr] = axi_wide_ar_queue.addr;

assign axi_rsp_src_id[NarrowB] = narrow_aw_buf_hdr_out.hdr.src_id;
assign axi_rsp_src_id[NarrowR] = narrow_ar_buf_hdr_out.hdr.src_id;
assign axi_rsp_src_id[WideB] = wide_aw_buf_hdr_out.hdr.src_id;
assign axi_rsp_src_id[WideR] = wide_ar_buf_hdr_out.hdr.src_id;

for (genvar ch = 0; ch < NumNWAxiChannels; ch++) begin : gen_route_comp
localparam nw_ch_e nw_ch = nw_ch_e'(ch);

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/floo_nw_chimney.sv#L648 

Localparam name does not match the naming convention defined by regex pattern: (([A-Z0-9]+[a-z0-9]*)+(_[0-9]+)?) [Style: constants] [parameter-name-style]
Raw output 
message:"Localparam name does not match the naming convention defined by regex pattern: (([A-Z0-9]+[a-z0-9]*)+(_[0-9]+)?) [Style: constants] [parameter-name-style]" location:{path:"./hw/floo_nw_chimney.sv" range:{start:{line:648 column:24}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
if (nw_ch == NarrowAw || nw_ch == NarrowAr ||
nw_ch == WideAw || nw_ch == WideAr) begin : gen_req_route_comp

// Translate the address from AXI requests to a destination ID
// (or route if `SourceRouting` is used)
floo_route_comp #(
.RouteCfg ( RouteCfg ),
.id_t ( id_t ),
.addr_t ( axi_addr_t ),
.addr_rule_t ( sam_rule_t ),
.route_t ( route_t )
) i_floo_req_route_comp (
.clk_i,
.rst_ni,
.route_table_i,
.addr_map_i ( Sam ),
.id_i ( id_t'('0) ),
.addr_i ( axi_req_addr[ch] ),
.route_o ( route_out[ch] ),
.id_o ( id_out[ch] )
);
end else if (RouteCfg.RouteAlgo == floo_pkg::SourceRouting &&
(nw_ch == NarrowB || nw_ch == NarrowR ||
nw_ch == WideB || nw_ch == WideR)) begin : gen_rsp_route_comp
// Generally, the source ID from the request is used to route back
// the responses. However, in the case of `SourceRouting`, the source ID
// first needs to be translated into a route.
floo_route_comp #(
.RouteCfg ( RouteCfg ),
.UseIdTable ( 1'b0 ), // Overwrite `RouteCfg`
.id_t ( id_t ),
.addr_t ( axi_addr_t ),
.addr_rule_t ( sam_rule_t ),
.route_t ( route_t )
) i_floo_rsp_route_comp (
.clk_i,
.rst_ni,
.route_table_i,
.addr_i ( '0 ),
.addr_map_i ( '0 ),
.id_i ( axi_rsp_src_id[ch] ),
.route_o ( route_out[ch] ),
.id_o ( id_out[ch] )
);
end
end

if (RouteCfg.RouteAlgo == floo_pkg::SourceRouting) begin : gen_route_field
floo_route_comp #(
.RouteCfg ( RouteCfg ),
.UseIdTable ( 1'b0 ), // Overwrite `RouteCfg`
.id_t ( id_t ),
.addr_t ( axi_addr_t ),
.addr_rule_t ( sam_rule_t ),
.route_t ( route_t )
) i_floo_rsp_route_comp [3:0] (
.clk_i,
.rst_ni,
.route_table_i,
.addr_i ( '{default: '0} ),
.addr_map_i ( '{default: '0} ),
.id_i ({
narrow_aw_buf_hdr_out.hdr.src_id, narrow_ar_buf_hdr_out.hdr.src_id,
wide_aw_buf_hdr_out.hdr.src_id, wide_ar_buf_hdr_out.hdr.src_id
}),
.route_o ({route_out[NarrowB], route_out[NarrowR], route_out[WideB], route_out[WideR]} ),
.id_o ({id_out[NarrowB], id_out[NarrowR], id_out[WideB], id_out[WideR]} )
);
assign route_out[NarrowW] = narrow_aw_id_q;
assign route_out[WideW] = wide_aw_id_q;
assign dst_id = route_out;
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102 changes: 61 additions & 41 deletions hw/floo_nw_vc_chimney.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -679,49 +679,69 @@ module floo_nw_vc_chimney #(
// ROUTING //
/////////////////

typedef axi_addr_t addr_t;

floo_route_comp #(
.RouteCfg ( RouteCfg ),
.id_t ( id_t ),
.addr_t ( addr_t ),
.addr_rule_t ( sam_rule_t ),
.route_t ( route_t )
) i_floo_req_route_comp [3:0] (
.clk_i,
.rst_ni,
.route_table_i,
.addr_map_i ( Sam ),
.id_i ( '0 ),
.addr_i ({
axi_narrow_aw_queue.addr, axi_narrow_ar_queue.addr,
axi_wide_aw_queue.addr, axi_wide_ar_queue.addr
}),
.route_o ({route_out[NarrowAw], route_out[NarrowAr], route_out[WideAw], route_out[WideAr]} ),
.id_o ({id_out[NarrowAw], id_out[NarrowAr],id_out[WideAw], id_out[WideAr]} )
);
axi_addr_t [NumNWAxiChannels-1:0] axi_req_addr;
id_t [NumNWAxiChannels-1:0] axi_rsp_src_id;

assign axi_req_addr[NarrowAw] = axi_narrow_aw_queue.addr;
assign axi_req_addr[NarrowAr] = axi_narrow_ar_queue.addr;
assign axi_req_addr[WideAw] = axi_wide_aw_queue.addr;
assign axi_req_addr[WideAr] = axi_wide_ar_queue.addr;

assign axi_rsp_src_id[NarrowB] = narrow_aw_buf_hdr_out.hdr.src_id;
assign axi_rsp_src_id[NarrowR] = narrow_ar_buf_hdr_out.hdr.src_id;
assign axi_rsp_src_id[WideB] = wide_aw_buf_hdr_out.hdr.src_id;
assign axi_rsp_src_id[WideR] = wide_ar_buf_hdr_out.hdr.src_id;

for (genvar ch = 0; ch < NumNWAxiChannels; ch++) begin : gen_route_comp
localparam nw_ch_e nw_ch = nw_ch_e'(ch);

Check warning on line 696 in hw/floo_nw_vc_chimney.sv

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[verible-verilog-lint] hw/floo_nw_vc_chimney.sv#L696 

Localparam name does not match the naming convention defined by regex pattern: (([A-Z0-9]+[a-z0-9]*)+(_[0-9]+)?) [Style: constants] [parameter-name-style]
Raw output 
message:"Localparam name does not match the naming convention defined by regex pattern: (([A-Z0-9]+[a-z0-9]*)+(_[0-9]+)?) [Style: constants] [parameter-name-style]" location:{path:"./hw/floo_nw_vc_chimney.sv" range:{start:{line:696 column:24}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
if (nw_ch == NarrowAw || nw_ch == NarrowAr ||
nw_ch == WideAw || nw_ch == WideAr) begin : gen_req_route_comp

// Translate the address from AXI requests to a destination ID
// (or route if `SourceRouting` is used)
floo_route_comp #(
.RouteCfg ( RouteCfg ),
.id_t ( id_t ),
.addr_t ( axi_addr_t ),
.addr_rule_t ( sam_rule_t ),
.route_t ( route_t )
) i_floo_req_route_comp (
.clk_i,
.rst_ni,
.route_table_i,
.addr_map_i ( Sam ),
.id_i ( id_t'('0) ),
.addr_i ( axi_req_addr[ch] ),
.route_o ( route_out[ch] ),
.id_o ( id_out[ch] )
);
end else if (RouteCfg.RouteAlgo == floo_pkg::SourceRouting &&
(nw_ch == NarrowB || nw_ch == NarrowR ||
nw_ch == WideB || nw_ch == WideR)) begin : gen_rsp_route_comp
// Generally, the source ID from the request is used to route back
// the responses. However, in the case of `SourceRouting`, the source ID
// first needs to be translated into a route.
floo_route_comp #(
.RouteCfg ( RouteCfg ),
.UseIdTable ( 1'b0 ), // Overwrite `RouteCfg`
.id_t ( id_t ),
.addr_t ( axi_addr_t ),
.addr_rule_t ( sam_rule_t ),
.route_t ( route_t )
) i_floo_rsp_route_comp (
.clk_i,
.rst_ni,
.route_table_i,
.addr_i ( '0 ),
.addr_map_i ( '0 ),
.id_i ( axi_rsp_src_id[ch] ),
.route_o ( route_out[ch] ),
.id_o ( id_out[ch] )
);
end
end

if (RouteCfg.RouteAlgo == floo_pkg::SourceRouting) begin : gen_route_field
floo_route_comp #(
.RouteCfg ( RouteCfg ),
.UseIdTable ( 1'b0 ), // Overwrite `RouteCfg`
.id_t ( id_t ),
.addr_t ( addr_t ),
.addr_rule_t ( sam_rule_t ),
.route_t ( route_t )
) i_floo_rsp_route_comp [3:0] (
.clk_i,
.rst_ni,
.route_table_i,
.addr_i ( '0 ),
.addr_map_i ( '0 ),
.id_i ({
narrow_aw_buf_hdr_out.hdr.src_id, narrow_ar_buf_hdr_out.hdr.src_id,
wide_aw_buf_hdr_out.hdr.src_id, wide_ar_buf_hdr_out.hdr.src_id
}),
.route_o ({route_out[NarrowB], route_out[NarrowR], route_out[WideB], route_out[WideR]} ),
.id_o ({id_out[NarrowB], id_out[NarrowR], id_out[WideB], id_out[WideR]} )
);
assign route_out[NarrowW] = narrow_aw_id_q;
assign route_out[WideW] = wide_aw_id_q;
assign dst_id = route_out;
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