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wip: Floo macros
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@fischeti
fischeti committed Sep 11, 2024
1 parent 091ee65 commit 2f2c99a
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433 changes: 207 additions & 226 deletions hw/floo_axi_chimney.sv
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2 changes: 1 addition & 1 deletion hw/floo_mesh.sv
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Expand Up @@ -104,7 +104,7 @@ import floo_pkg::*;
.NumRoutes ( 5 ),
.flit_t ( flit_t ),
.RouteAlgo ( RouteAlgo ),
.ChannelFifoDepth( 2 ),
.InFifoDepth( 2 ),
.IdWidth ( $bits(xy_id_t) ),
.id_t ( xy_id_t ),
.addr_rule_t ( logic ),
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2 changes: 1 addition & 1 deletion hw/floo_mesh_ruche.sv
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Expand Up @@ -156,7 +156,7 @@ module floo_mesh_ruche
.NumRoutes ( NumRoutes ),
.flit_t ( flit_t ),
.RouteAlgo ( RouteAlgo ),
.ChannelFifoDepth( 2 ),
.InFifoDepth( 2 ),
.IdWidth ( $bits(xy_id_t) ),
.id_t ( xy_id_t ),
.addr_rule_t ( logic ),
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587 changes: 282 additions & 305 deletions hw/floo_narrow_wide_chimney.sv
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93 changes: 57 additions & 36 deletions hw/floo_narrow_wide_router.sv
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Expand Up @@ -4,24 +4,30 @@
//
// Author: Tim Fischer <[email protected]>

`include "axi/typedef.svh"
`include "floo_noc/typedef.svh"

/// Wrapper of a multi-link router for narrow and wide links
module floo_narrow_wide_router
import floo_pkg::*;
import floo_narrow_wide_pkg::*;
#(
parameter int unsigned NumRoutes = NumDirections,
parameter int unsigned NumInputs = NumRoutes,
parameter int unsigned NumOutputs = NumRoutes,
parameter int unsigned ChannelFifoDepth = 0,
parameter int unsigned OutputFifoDepth = 0,
parameter route_algo_e RouteAlgo = XYRouting,
parameter bit XYRouteOpt = 1'b1,
/// Used for ID-based and XY routing
parameter int unsigned IdWidth = 0,
parameter type id_t = logic[IdWidth-1:0],
/// Used for ID-based routing
parameter int unsigned NumAddrRules = 0,
parameter type addr_rule_t = logic
module floo_nw_router #(

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[verible-verilog-lint] hw/floo_narrow_wide_router.sv#L11 

Declared module does not match the first dot-delimited component of file name: "floo_narrow_wide_router" [Style: file-names] [module-filename]
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message:"Declared module does not match the first dot-delimited component of file name: \"floo_narrow_wide_router\" [Style: file-names] [module-filename]" location:{path:"./hw/floo_narrow_wide_router.sv" range:{start:{line:11 column:8}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:11 column:8} end:{line:12}} text:"module floo_narrow_wide_router #(\n"}
parameter floo_pkg::axi_cfg_t AxiCfgN = '0,
parameter floo_pkg::axi_cfg_t AxiCfgW = '0,
parameter floo_pkg::route_algo_e RouteAlgo = floo_pkg::XYRouting,
parameter int unsigned NumRoutes = 0,
parameter int unsigned NumInputs = NumRoutes,
parameter int unsigned NumOutputs = NumRoutes,
parameter int unsigned InFifoDepth = 0,
parameter int unsigned OutFifoDepth = 0,
parameter bit XYRouteOpt = 1'b1,
/// Used for ID-based and XY routing
parameter int unsigned IdWidth = 0,
parameter type id_t = logic[IdWidth-1:0],
parameter type hdr_t = logic,
/// Used for ID-based routing
parameter int unsigned NumAddrRules = 0,
parameter type addr_rule_t = logic,
parameter type floo_req_t = logic,
parameter type floo_rsp_t = logic,
parameter type floo_wide_t = logic
) (
input logic clk_i,
input logic rst_ni,
Expand All @@ -34,10 +40,25 @@ module floo_narrow_wide_router
input floo_rsp_t [NumOutputs-1:0] floo_rsp_i,
output floo_req_t [NumOutputs-1:0] floo_req_o,
output floo_rsp_t [NumInputs-1:0] floo_rsp_o,
input floo_wide_t [NumRoutes-1:0] floo_wide_i,
output floo_wide_t [NumRoutes-1:0] floo_wide_o
input floo_wide_t [NumRoutes-1:0] floo_wide_i,
output floo_wide_t [NumRoutes-1:0] floo_wide_o
);

typedef logic [AxiCfgN.AddrWidth-1:0] axi_addr_t;
typedef logic [AxiCfgN.InIdWidth-1:0] axi_narrow_in_id_t;
typedef logic [AxiCfgN.UserWidth-1:0] axi_narrow_user_t;
typedef logic [AxiCfgN.DataWidth-1:0] axi_narrow_data_t;
typedef logic [AxiCfgN.DataWidth/8-1:0] axi_narrow_strb_t;
typedef logic [AxiCfgW.InIdWidth-1:0] axi_wide_in_id_t;
typedef logic [AxiCfgW.UserWidth-1:0] axi_wide_user_t;
typedef logic [AxiCfgW.DataWidth-1:0] axi_wide_data_t;
typedef logic [AxiCfgW.DataWidth/8-1:0] axi_wide_strb_t;

// (Re-) definitons of `axi_in` and `floo` types, for transport
`AXI_TYPEDEF_ALL_CT(axi_narrow, axi_narrow_req_t, axi_narrow_rsp_t, axi_addr_t, axi_narrow_in_id_t, axi_narrow_data_t, axi_narrow_strb_t, axi_narrow_user_t)

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[verible-verilog-lint] hw/floo_narrow_wide_router.sv#L58 

Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]
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message:"Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]" location:{path:"./hw/floo_narrow_wide_router.sv" range:{start:{line:58 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
`AXI_TYPEDEF_ALL_CT(axi_wide, axi_wide_req_t, axi_wide_rsp_t, axi_addr_t, axi_wide_in_id_t, axi_wide_data_t, axi_wide_strb_t, axi_wide_user_t)

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[verible-verilog-lint] hw/floo_narrow_wide_router.sv#L59 

Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]
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message:"Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]" location:{path:"./hw/floo_narrow_wide_router.sv" range:{start:{line:59 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
`FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow, axi_wide, AxiCfgN, AxiCfgW, hdr_t)

floo_req_chan_t [NumInputs-1:0] req_in;
floo_rsp_chan_t [NumInputs-1:0] rsp_out;
floo_req_chan_t [NumOutputs-1:0] req_out;
Expand Down Expand Up @@ -78,19 +99,19 @@ module floo_narrow_wide_router
end

floo_router #(
.NumPhysChannels ( 1 ),
.NumVirtChannels ( 1 ),
.NumInput ( NumInputs ),
.NumOutput ( NumOutputs ),
.flit_t ( floo_req_generic_flit_t ),
.ChannelFifoDepth ( ChannelFifoDepth ),
.OutputFifoDepth ( OutputFifoDepth ),
.RouteAlgo ( RouteAlgo ),
.XYRouteOpt ( XYRouteOpt ),
.IdWidth ( IdWidth ),
.id_t ( id_t ),
.NumAddrRules ( NumAddrRules ),
.addr_rule_t ( addr_rule_t )
.NumPhysChannels ( 1 ),
.NumVirtChannels ( 1 ),
.NumInput ( NumInputs ),
.NumOutput ( NumOutputs ),
.flit_t ( floo_req_chan_t ),
.InFifoDepth ( InFifoDepth ),
.OutFifoDepth ( OutFifoDepth ),
.RouteAlgo ( RouteAlgo ),
.XYRouteOpt ( XYRouteOpt ),
.IdWidth ( IdWidth ),
.id_t ( id_t ),
.NumAddrRules ( NumAddrRules ),
.addr_rule_t ( addr_rule_t )
) i_req_floo_router (
.clk_i,
.rst_ni,
Expand All @@ -111,8 +132,8 @@ module floo_narrow_wide_router
.NumVirtChannels ( 1 ),
.NumInput ( NumInputs ),
.NumOutput ( NumOutputs ),
.ChannelFifoDepth ( ChannelFifoDepth ),
.OutputFifoDepth ( OutputFifoDepth ),
.InFifoDepth ( InFifoDepth ),
.OutFifoDepth ( OutFifoDepth ),
.RouteAlgo ( RouteAlgo ),
.XYRouteOpt ( XYRouteOpt ),
.IdWidth ( IdWidth ),
Expand Down Expand Up @@ -140,8 +161,8 @@ module floo_narrow_wide_router
.NumVirtChannels ( 1 ),
.NumRoutes ( NumRoutes ),
.flit_t ( floo_wide_generic_flit_t ),
.ChannelFifoDepth ( ChannelFifoDepth ),
.OutputFifoDepth ( OutputFifoDepth ),
.InFifoDepth ( InFifoDepth ),
.OutFifoDepth ( OutFifoDepth ),
.RouteAlgo ( RouteAlgo ),
.XYRouteOpt ( XYRouteOpt ),
.IdWidth ( IdWidth ),
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162 changes: 162 additions & 0 deletions hw/floo_pkg.sv
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Expand Up @@ -38,4 +38,166 @@ package floo_pkg;
NoRoB
} rob_type_e;

typedef enum logic [2:0] {
AxiAw = 3'd0,
AxiW = 3'd1,
AxiAr = 3'd2,
AxiB = 3'd3,
AxiR = 3'd4,
NumAxiChannels = 3'd5
} axi_ch_e;

typedef enum logic [3:0] {
NarrowAw = 4'd0,
NarrowW = 4'd1,
NarrowAr = 4'd2,
WideAr = 4'd3,
NarrowB = 4'd4,
NarrowR = 4'd5,
WideB = 4'd6,
WideAw = 4'd7,
WideW = 4'd8,
WideR = 4'd9,
NumNWAxiChannels = 4'd10
} nw_ch_e;

typedef enum logic [1:0] {
FlooReq = 2'd0,
FlooRsp = 2'd1,
FlooWide = 2'd2
} floo_chan_e;

typedef struct packed {
int unsigned AddrWidth;
int unsigned DataWidth;
int unsigned UserWidth;
int unsigned InIdWidth;
int unsigned OutIdWidth;
} axi_cfg_t;

typedef struct packed {
route_algo_e RouteAlgo;
bit UseIdTable;
int unsigned XYAddrOffsetX;
int unsigned XYAddrOffsetY;
int unsigned IdAddrOffset;
int unsigned NumAddrRules;
int unsigned SamNumRules;
int unsigned NumRoutes;
} route_cfg_t;

typedef struct packed {
bit EnSbrPort;
bit EnMgrPort;
int unsigned MaxTxns;
int unsigned MaxUniqueIds;
int unsigned MaxTxnsPerId;
rob_type_e BRoBType;
int unsigned BRoBDepth;
rob_type_e RRoBType;
int unsigned RRoBDepth;
bit CutAx;
bit CutRsp;
} chimney_cfg_t;

localparam chimney_cfg_t ChimneyDefaultCfg = '{
EnSbrPort: 1'b1,
EnMgrPort: 1'b1,
MaxTxns: 32,
MaxUniqueIds: 1,
MaxTxnsPerId: 32,
BRoBType: NoRoB,
BRoBDepth: 0,
RRoBType: NoRoB,
RRoBDepth: 0,
CutAx: 1'b0,
CutRsp: 1'b0
};

localparam route_cfg_t RouteDefaultCfg = '{
RouteAlgo: XYRouting,
UseIdTable: 1'b0,
XYAddrOffsetX: 0,
XYAddrOffsetY: 0,
IdAddrOffset: 0,
NumAddrRules: 0,
SamNumRules: 0,
NumRoutes: 0
};

function automatic floo_chan_e axi_chan_mapping(axi_ch_e ch);
if (ch == AxiAw || ch == AxiW || ch == AxiAr) begin
return FlooReq;
end else begin
return FlooRsp;
end
endfunction

function automatic floo_chan_e nw_chan_mapping(nw_ch_e ch);
if (ch == NarrowAw || ch == NarrowW || ch == NarrowAr || ch == WideAr) begin
return FlooReq;
end else if (ch == WideAw || ch == WideW || ch == WideR) begin
return FlooWide;
end else begin
return FlooRsp;
end
endfunction

function automatic int unsigned get_axi_chan_width(axi_cfg_t cfg, axi_ch_e ch);
case (ch)

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[verible-verilog-lint] hw/floo_pkg.sv#L147 

Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default]
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message:"Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default]" location:{path:"./hw/floo_pkg.sv" range:{start:{line:147 column:5}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
AxiAw: return axi_pkg::aw_width(cfg.AddrWidth, cfg.InIdWidth, cfg.UserWidth);
AxiW: return axi_pkg::w_width(cfg.DataWidth, cfg.UserWidth);
AxiB: return axi_pkg::b_width(cfg.InIdWidth, cfg.UserWidth);
AxiAr: return axi_pkg::ar_width(cfg.AddrWidth, cfg.InIdWidth, cfg.UserWidth);
AxiR: return axi_pkg::r_width(cfg.DataWidth, cfg.InIdWidth, cfg.UserWidth);
endcase
endfunction

function automatic int unsigned get_nw_chan_width(axi_cfg_t cfg_n, axi_cfg_t cfg_w, nw_ch_e ch);
case (ch)

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[verible-verilog-lint] hw/floo_pkg.sv#L157 

Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default]
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message:"Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default]" location:{path:"./hw/floo_pkg.sv" range:{start:{line:157 column:5}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
NarrowAw: return axi_pkg::aw_width(cfg_n.AddrWidth, cfg_n.InIdWidth, cfg_n.UserWidth);
NarrowW: return axi_pkg::w_width(cfg_n.DataWidth, cfg_n.UserWidth);
NarrowAr: return axi_pkg::ar_width(cfg_n.AddrWidth, cfg_n.InIdWidth, cfg_n.UserWidth);
NarrowB: return axi_pkg::b_width(cfg_n.InIdWidth, cfg_n.UserWidth);
NarrowR: return axi_pkg::r_width(cfg_n.DataWidth, cfg_n.InIdWidth, cfg_n.UserWidth);
WideAw: return axi_pkg::aw_width(cfg_w.AddrWidth, cfg_w.InIdWidth, cfg_w.UserWidth);
WideW: return axi_pkg::w_width(cfg_w.DataWidth, cfg_w.UserWidth);
WideR: return axi_pkg::r_width(cfg_w.DataWidth, cfg_w.InIdWidth, cfg_w.UserWidth);
WideAr: return axi_pkg::ar_width(cfg_w.AddrWidth, cfg_w.InIdWidth, cfg_w.UserWidth);
WideB: return axi_pkg::b_width(cfg_w.InIdWidth, cfg_w.UserWidth);
endcase
endfunction

function automatic int unsigned get_max_axi_payload_bits(axi_cfg_t cfg, floo_chan_e ch);
int unsigned max_payload_bits = 0;
for (int unsigned i = 0; i < NumAxiChannels; i++) begin
if (axi_chan_mapping(axi_ch_e'(i)) == ch) begin
if (get_axi_chan_width(cfg, axi_ch_e'(i)) > max_payload_bits) begin
max_payload_bits = get_axi_chan_width(cfg, axi_ch_e'(i));
end
end
end
return max_payload_bits + 1; // +1 because we need at least one `rsvd` bit
endfunction

function automatic int unsigned get_max_nw_payload_bits(axi_cfg_t cfg_n, axi_cfg_t cfg_w, floo_chan_e ch);

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Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]
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message:"Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]" location:{path:"./hw/floo_pkg.sv" range:{start:{line:183 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
int unsigned max_payload_bits = 0;
for (int unsigned i = 0; i < NumNWAxiChannels; i++) begin
if (nw_chan_mapping(nw_ch_e'(i)) == ch) begin
if (get_nw_chan_width(cfg_n, cfg_w, nw_ch_e'(i)) > max_payload_bits) begin
max_payload_bits = get_nw_chan_width(cfg_n, cfg_w, nw_ch_e'(i));
end
end
end
return max_payload_bits + 1; // +1 because we need at least one `rsvd` bit
endfunction

function automatic int unsigned get_axi_rsvd_bits(axi_cfg_t cfg, axi_ch_e ch);
return get_max_axi_payload_bits(cfg, axi_chan_mapping(ch)) - get_axi_chan_width(cfg, ch);
endfunction

function automatic int unsigned get_nw_rsvd_bits(axi_cfg_t cfg_n, axi_cfg_t cfg_w, nw_ch_e ch);
return get_max_nw_payload_bits(cfg_n, cfg_w, nw_chan_mapping(ch)) - get_nw_chan_width(cfg_n, cfg_w, ch);

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Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]
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message:"Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]" location:{path:"./hw/floo_pkg.sv" range:{start:{line:200 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
endfunction

endpackage
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