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lint: System Verilog sources
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fischeti committed Sep 27, 2023
1 parent c63448c commit 5b06f43
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion src/floo_rob_wrapper.sv
Original file line number Diff line number Diff line change
Expand Up @@ -171,7 +171,7 @@ module floo_rob_wrapper
.pop_i ( pop && rsp_ready_i ) // Only pop on handshake
);

end else begin
end else begin : gen_error
$error("Unknown RoB type %0d", RoBType);
end

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