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| // | ||
| // Lukas Berner <[email protected]> | ||
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| `include "common_cells/assertions.svh" | ||
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| /// Accepts flits from the input port and stores them in a FIFO. | ||
| module floo_input_port #( | ||
| parameter type flit_t = logic, | ||
| parameter type hdr_t = logic, | ||
| parameter int HdrLength = $bits(hdr_t), | ||
| parameter int DataLength = $bits(flit_t) - HdrLength, | ||
| parameter type flit_payload_t = logic[DataLength-1:0], | ||
| parameter int NumVC = 4, | ||
| parameter int NumVCWidth = 2, | ||
| parameter int VCDepth = 3, | ||
| parameter int DeeperVCId = 0, | ||
| parameter int DeeperVCDepth = 2 | ||
| /// Types of the flit, header and payload | ||
| parameter type flit_t = logic, | ||
| parameter type hdr_t = logic, | ||
| parameter type payload_t = logic, | ||
| /// Number of virtual channels | ||
| parameter int unsigned NumVC = 32'd0, | ||
| /// Width of the VC index | ||
| parameter int unsigned VCIdxWidth = 32'd0, | ||
| /// Depth of the VC FIFOs | ||
| parameter int unsigned VCDepth = 32'd0, | ||
| /// Deeper FIFO for a specific VC | ||
| parameter int unsigned DeeperVCId = 32'd0, | ||
| /// Depth of the deeper FIFO | ||
| parameter int unsigned DeeperVCDepth = 32'd0 | ||
| ) ( | ||
| input logic clk_i, | ||
| input logic rst_ni, | ||
| // input from other router or local port | ||
| output logic credit_v_o, | ||
| output logic [NumVCWidth-1:0] credit_id_o, | ||
| input logic data_v_i, | ||
| input flit_t data_i, | ||
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| output logic [NumVC-1:0] vc_ctrl_head_v_o, | ||
| output hdr_t [NumVC-1:0] vc_ctrl_head_o, | ||
| output flit_payload_t [NumVC-1:0] vc_data_head_o, | ||
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| /// input from other router or local port | ||
| output logic credit_valid_o, | ||
| output logic [VCIdxWidth-1:0] credit_id_o, | ||
| input logic data_valid_i, | ||
| input flit_t data_i, | ||
| /// output to router | ||
| output logic [NumVC-1:0] vc_hdr_valid_o, | ||
| output hdr_t [NumVC-1:0] vc_hdr_o, | ||
| output payload_t [NumVC-1:0] vc_data_o, | ||
| // input pop flit ctrl fifo (comes from SA stage) | ||
| input logic read_enable_sa_stage_i, | ||
| input logic [NumVC-1:0] read_vc_id_oh_sa_stage_i, | ||
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| input logic read_enable_sa_stage_i, | ||
| input logic [NumVC-1:0] read_vc_id_oh_sa_stage_i, | ||
| // input pop flit ctrl fifo (comes from ST stage) | ||
| input logic read_enable_st_stage_i, | ||
| input logic [NumVC-1:0] read_vc_id_oh_st_stage_i | ||
| input logic read_enable_st_stage_i, | ||
| input logic [NumVC-1:0] read_vc_id_oh_st_stage_i | ||
| ); | ||
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| logic [NumVC-1:0] data_v_i_oh; | ||
| logic [NumVC-1:0] remove_ctrl_head; | ||
| logic [NumVC-1:0] remove_data_head; | ||
| logic [NumVC-1:0] data_valid_i_oh; | ||
| logic [NumVC-1:0] remove_hdr; | ||
| logic [NumVC-1:0] remove_data; | ||
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| // where to add data | ||
| // One-hot encoding of valid data | ||
| always_comb begin | ||
| data_v_i_oh = '0; | ||
| if(data_v_i) begin | ||
| data_v_i_oh[data_i.hdr.vc_id[NumVCWidth-1:0]] = 1'b1; | ||
| data_valid_i_oh = '0; | ||
| if(data_valid_i) begin | ||
| data_valid_i_oh[data_i.hdr.vc_id[VCIdxWidth-1:0]] = 1'b1; | ||
| end | ||
| end | ||
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| // when to remove from fifo | ||
| // When to remove from fifo | ||
| always_comb begin | ||
| // remove ctrl at SA stage | ||
| remove_ctrl_head = '0; | ||
| if(read_enable_sa_stage_i) | ||
| remove_ctrl_head = read_vc_id_oh_sa_stage_i; | ||
| // remove data at ST stage | ||
| remove_data_head = '0; | ||
| if(read_enable_st_stage_i) | ||
| remove_data_head = read_vc_id_oh_st_stage_i; | ||
| // Remove ctrl at SA stage | ||
| remove_hdr = '0; | ||
| if(read_enable_sa_stage_i) begin | ||
| remove_hdr = read_vc_id_oh_sa_stage_i; | ||
| end | ||
| // Remove data at ST stage | ||
| remove_data = '0; | ||
| if(read_enable_st_stage_i) begin | ||
| remove_data = read_vc_id_oh_st_stage_i; | ||
| end | ||
| end | ||
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| // data fifo -> hdr is always before payload in flits | ||
| for(genvar v_chan = 0; v_chan < NumVC; v_chan++) begin: gen_data_fifos | ||
| // Data Fifo | ||
| for(genvar vc = 0; vc < NumVC; vc++) begin: gen_data_fifos | ||
| localparam int unsigned Depth = (vc == DeeperVCId) ? DeeperVCDepth : VCDepth; | ||
| floo_input_fifo #( | ||
| .Depth (v_chan == DeeperVCId ? DeeperVCDepth : VCDepth), | ||
| .type_t (flit_payload_t) | ||
| .Depth ( Depth ), | ||
| .type_t ( payload_t ) | ||
| ) i_data_fifo ( | ||
| .clk_i, | ||
| .rst_ni, | ||
| .data_i (data_i [DataLength-1:0]), | ||
| .valid_i (data_v_i_oh [v_chan]), | ||
| .data_o (vc_data_head_o [v_chan]), | ||
| .valid_o (), | ||
| .ready_i (remove_data_head [v_chan]) | ||
| .data_i ( data_i.payload ), | ||
| .valid_i ( data_valid_i_oh[vc] ), | ||
| .data_o ( vc_data_o [vc] ), | ||
| .valid_o ( ), | ||
| .ready_i ( remove_data[vc] ) | ||
| ); | ||
| end | ||
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| // ctrl fifo -> hdr is always before payload in flits | ||
| for(genvar v_chan = 0; v_chan < NumVC; v_chan++) begin: gen_ctrl_fifos | ||
| floo_input_fifo #( | ||
| .Depth (v_chan == DeeperVCId ? DeeperVCDepth : VCDepth), | ||
| .type_t (hdr_t) | ||
| ) i_data_fifo ( | ||
| .clk_i, | ||
| .rst_ni, | ||
| .data_i (data_i [DataLength+HdrLength-1:DataLength]), | ||
| .valid_i (data_v_i_oh [v_chan]), | ||
| .data_o (vc_ctrl_head_o [v_chan]), | ||
| .valid_o (vc_ctrl_head_v_o [v_chan]), | ||
| .ready_i (remove_ctrl_head [v_chan]) | ||
| ); | ||
| .Depth ( Depth ), | ||
| .type_t ( hdr_t ) | ||
| ) i_hdr_fifo ( | ||
| .clk_i, | ||
| .rst_ni, | ||
| .data_i ( data_i.hdr ), | ||
| .valid_i ( data_valid_i_oh[vc] ), | ||
| .data_o ( vc_hdr_o[vc] ), | ||
| .valid_o ( vc_hdr_valid_o[vc] ), | ||
| .ready_i ( remove_hdr [vc] ) | ||
| ); | ||
| end | ||
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| assign credit_v_o = read_enable_st_stage_i; //could also be from sa stage | ||
| logic [NumVCWidth-1:0][NumVC-1:0] id_mask; | ||
| logic [VCIdxWidth-1:0][NumVC-1:0] id_mask; | ||
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| // Could also be from sa stage | ||
| assign credit_valid_o = read_enable_st_stage_i; | ||
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| //extract credit_id from onehot: create id mask | ||
| for(genvar i = 0; i < NumVCWidth; i++) begin : gen_id_mask_NumVCWidth | ||
| // Extract `credit_id` from onehot: create id mask | ||
| for(genvar i = 0; i < VCIdxWidth; i++) begin : gen_id_mask_NumVCWidth | ||
| for(genvar j = 0; j < NumVC; j++) begin : gen_id_mask_NumVC | ||
| assign id_mask[i][j] = (j/(2**i)) % 2; | ||
| end | ||
| end | ||
| //mask looks like this: N_Input = 3: (0,0) is first bit | ||
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| // Mask looks like this: N_Input = 3: (0,0) is first bit | ||
| // 0 0 0 // 1 0 0 // 0 1 0 // 1 1 0 // 0 0 1 // 1 0 1 // 0 1 1 // 1 1 1 | ||
| // use mask to get credit_id | ||
| for(genvar i = 0; i < NumVCWidth; i++) begin : gen_get_credit_id | ||
| // Use mask to get credit_id | ||
| for(genvar i = 0; i < VCIdxWidth; i++) begin : gen_get_credit_id | ||
| assign credit_id_o[i] = |(read_vc_id_oh_st_stage_i & id_mask[i]); | ||
| end | ||
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