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try to pass linting check
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sem24f5 Lukas Berner (bernerl) committed Mar 4, 2024
1 parent 8201b1a commit 9ae0914
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Showing 6 changed files with 18 additions and 13 deletions.
2 changes: 1 addition & 1 deletion hw/floo_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@ package floo_pkg;
L1 = 3'd5,
L2 = 3'd6,
L3 = 3'd7
} route_dir_e; // i see that this is nasty, but i cannot work with eject (local) being 0, since there might be more than one local port
} route_dir_e; // this is nasty, but there might be more than one local port

typedef enum {
RucheNorth = 'd5,
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2 changes: 1 addition & 1 deletion hw/floo_vc_router.sv
Original file line number Diff line number Diff line change
Expand Up @@ -95,7 +95,7 @@ logic [NumPorts-1:0][NumVCWidth-1:0] sa_local_vc_id;
// 1 input ports
// =============

for (genvar i = 0; i < NumPorts; i++) begin
for (genvar i = 0; i < NumPorts; i++) begin : gen_input_ports
floo_input_port #(
.flit_t,
.flit_payload_t,
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8 changes: 7 additions & 1 deletion hw/tb/tb_floo_vc_router.sv
Original file line number Diff line number Diff line change
@@ -1,3 +1,9 @@
// Copyright 2024 ETH Zurich and University of Bologna.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51
//
// Lukas Berner <[email protected]>

/*test ideas:
1) connectivity from each input vs to each output vc, lookahead is set correctly on output
2) FVADA working correctly: forward to different vc if prioritized one is not free -> lookahead still set correctly
Expand All @@ -7,4 +13,4 @@
*/
*/
4 changes: 2 additions & 2 deletions hw/vc_router_util/floo_input_port.sv
Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@ always_comb begin
end

// data fifo -> hdr is always before payload in flits
for(genvar v_chan = 0; v_chan < NumVC; v_chan++) begin: gen_data_fifo
for(genvar v_chan = 0; v_chan < NumVC; v_chan++) begin: gen_data_fifos
stream_fifo_optimal_wrap #(
.Depth (VCDepth),
.type_t (flit_payload_t)
Expand All @@ -69,7 +69,7 @@ for(genvar v_chan = 0; v_chan < NumVC; v_chan++) begin: gen_data_fifo
end

// ctrl fifo -> hdr is always before payload in flits
for(genvar v_chan = 0; v_chan < NumVC; v_chan++) begin: gen_ctrl_fifo
for(genvar v_chan = 0; v_chan < NumVC; v_chan++) begin: gen_ctrl_fifos
stream_fifo_optimal_wrap #(
.Depth (VCDepth),
.type_t (hdr_t)
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8 changes: 4 additions & 4 deletions hw/vc_router_util/floo_mux.sv
Original file line number Diff line number Diff line change
Expand Up @@ -19,14 +19,14 @@ module floo_mux
logic[DataWidth-1:0][NumInputs-1:0] transposed_data;
logic[DataWidth-1:0][NumInputs-1:0] select_mat;

for(genvar i = 0 ; i < DataWidth; i++) begin
for(genvar j = 0 ; j < NumInputs; j++) begin
for(genvar i = 0 ; i < DataWidth; i++) begin : gen_transpose_DataWidth
for(genvar j = 0 ; j < NumInputs; j++) begin : gen_transpose_NumInputs
assign transposed_data[i][j] = data_i[j][i];
end
end

for(genvar i = 0; i < DataWidth; i++) begin
for(genvar i = 0; i < DataWidth; i++) begin : gen_select_data
assign data_o[i] = |(transposed_data[i] & sel_i);
end

endmodule
endmodule
7 changes: 3 additions & 4 deletions hw/vc_router_util/floo_rr_arbiter.sv
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,6 @@ module floo_rr_arbiter #(
);
genvar i, j;
if(NumInputs == 1) begin:

assign grant_o = req_i;
assign grant_id_o = 0;
end else begin:
Expand All @@ -44,15 +43,15 @@ module floo_rr_arbiter #(
assign dereordered_selected_req = right_rotate_helper[NumInputs*2-1-:NumInputs];

//extract id from onehot: create id mask
for(i = 0; i < NumInputsWidth; i++) begin
for(j = 0; j < NumInputs; j++) begin
for(i = 0; i < NumInputsWidth; i++) begin : gen_id_mask_NumInputsWidth
for(j = 0; j < NumInputs; j++) begin : gen_id_mask_NumInputs
assign id_mask[i][j] = (j/(2**i)) % 2;
end
end
//mask looks like this: N_Input = 3: (0,0) is first bit
// 0 0 0 // 1 0 0 // 0 1 0 // 1 1 0 // 0 0 1 // 1 0 1 // 0 1 1 // 1 1 1
// use mask to get req_id
for(i = 0; i < NumInputsWidth; i++) begin
for(i = 0; i < NumInputsWidth; i++) begin : gen_get_selected_req_id
assign selected_req_id[i] = |(dereordered_selected_req & id_mask[i]);
end

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