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floogen(pkg): Refer rsvd as payload in generic flit types
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fischeti committed May 31, 2024
1 parent 1997224 commit cb417ae
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Showing 6 changed files with 13 additions and 13 deletions.
2 changes: 1 addition & 1 deletion floogen/model/link.py
Original file line number Diff line number Diff line change
Expand Up @@ -109,7 +109,7 @@ def render_flit(cls, protocols):
for phys_ch, size in link_sizes.items():
struct_dict = {
"hdr": "hdr_t",
"rsvd": f"logic[{size-1}:0]",
"payload": f"logic[{size-1}:0]",
}
string += sv_struct_typedef(f"floo_{phys_ch}_generic_flit_t", struct_dict)
return string
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4 changes: 2 additions & 2 deletions hw/floo_axi_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -139,12 +139,12 @@ package floo_axi_pkg;

typedef struct packed {
hdr_t hdr;
logic [73:0] rsvd;
logic [73:0] payload;
} floo_req_generic_flit_t;

typedef struct packed {
hdr_t hdr;
logic [70:0] rsvd;
logic [70:0] payload;
} floo_rsp_generic_flit_t;


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6 changes: 3 additions & 3 deletions hw/floo_narrow_wide_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -206,17 +206,17 @@ package floo_narrow_wide_pkg;

typedef struct packed {
hdr_t hdr;
logic [87:0] rsvd;
logic [87:0] payload;
} floo_req_generic_flit_t;

typedef struct packed {
hdr_t hdr;
logic [71:0] rsvd;
logic [71:0] payload;
} floo_rsp_generic_flit_t;

typedef struct packed {
hdr_t hdr;
logic [577:0] rsvd;
logic [577:0] payload;
} floo_wide_generic_flit_t;


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6 changes: 3 additions & 3 deletions hw/floo_vc_narrow_wide_chimney.sv
Original file line number Diff line number Diff line change
Expand Up @@ -928,7 +928,7 @@ module floo_vc_narrow_wide_chimney
.valid_i ( floo_req_arb_req_in ),
.data_i ( floo_req_arb_in ),
.ready_o ( floo_req_arb_gnt_out ),
.data_o ( {floo_req_arb_sel_hdr, floo_req_o.req.generic.rsvd}),
.data_o ( {floo_req_arb_sel_hdr, floo_req_o.req.generic.payload}),
.ready_i ( floo_req_o.valid ),
.valid_o ( floo_req_arb_v )
);
Expand All @@ -942,7 +942,7 @@ module floo_vc_narrow_wide_chimney
.valid_i ( floo_rsp_arb_req_in ),
.data_i ( floo_rsp_arb_in ),
.ready_o ( floo_rsp_arb_gnt_out ),
.data_o ( {floo_rsp_arb_sel_hdr,floo_rsp_o.rsp.generic.rsvd}),
.data_o ( {floo_rsp_arb_sel_hdr,floo_rsp_o.rsp.generic.payload}),
.ready_i ( floo_rsp_o.valid ),
.valid_o ( floo_rsp_arb_v )
);
Expand All @@ -956,7 +956,7 @@ module floo_vc_narrow_wide_chimney
.valid_i ( floo_wide_arb_req_in ),
.data_i ( floo_wide_arb_in ),
.ready_o ( floo_wide_arb_gnt_out ),
.data_o ( {floo_wide_arb_sel_hdr, floo_wide_o.wide.generic.rsvd}),
.data_o ( {floo_wide_arb_sel_hdr, floo_wide_o.wide.generic.payload}),
.ready_i ( floo_wide_o.valid ),
.valid_o ( floo_wide_arb_v )
);
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4 changes: 2 additions & 2 deletions hw/tb/tb_floo_router.sv
Original file line number Diff line number Diff line change
Expand Up @@ -116,7 +116,7 @@ module tb_floo_router;
rand_data.data_mod_id_c.constraint_mode(1);
if (rand_data.randomize()) begin
automatic floo_req_generic_flit_t next_flit = '0;
next_flit.rsvd = rand_data.data;
next_flit.payload = rand_data.data;
next_flit.hdr.src_id = port;
next_flit.hdr.dst_id = stimuli.id;
next_flit.hdr.last = j == stimuli.len-1;
Expand Down Expand Up @@ -343,7 +343,7 @@ module tb_floo_router;
golden = golden_queue[result.hdr.src_id][virt_channel][port].pop_front();
end

if (result.rsvd != golden.rsvd) begin
if (result.payload != golden.payload) begin
$error("ERROR! Mismatch for port %d channel %d (from %d, target port %d)",
port, virt_channel, result.hdr.src_id, result.hdr.dst_id);
end
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4 changes: 2 additions & 2 deletions hw/vc_router_util/floo_vc_router_switch.sv
Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,7 @@ if(RouteAlgo != XYRouting) begin : gen_switch_not_XY_routing_optimized
// dont need to check bits on diagonal
if(out_port != in_port) begin : gen_nXYopt_out_neq_in
if(inport_id_oh_per_output_i[out_port][in_port]) begin : gen_nXYopt_found_match
data_o[out_port].rsvd = data_head_per_inport[in_port];
data_o[out_port].payload = data_head_per_inport[in_port];
data_o[out_port].hdr.rob_req = ctrl_head_per_inport_i[in_port].rob_req;
data_o[out_port].hdr.rob_idx = ctrl_head_per_inport_i[in_port].rob_idx;
data_o[out_port].hdr.dst_id = ctrl_head_per_inport_i[in_port].dst_id;
Expand All @@ -78,7 +78,7 @@ end else begin : gen_switch_XY_routing_optimized
(out_port == West && (in_port == South || in_port == North))
)) begin : gen_XYopt_possible_connection
if(inport_id_oh_per_output_i[out_port][in_port]) begin : gen_nXYopt_found_match
data_o[out_port].rsvd = data_head_per_inport[in_port];
data_o[out_port].payload = data_head_per_inport[in_port];
data_o[out_port].hdr.rob_req = ctrl_head_per_inport_i[in_port].rob_req;
data_o[out_port].hdr.rob_idx = ctrl_head_per_inport_i[in_port].rob_idx;
data_o[out_port].hdr.dst_id = ctrl_head_per_inport_i[in_port].dst_id;
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