routing: Add source-based routing algorithm #30

fischeti · 2024-02-25T10:21:24Z

This PR adds source-based routing algorithm support for the routers and the chimneys. The routing is based on consumption of the route (i.e. shifting the route by the number of ports of each router). The route needs to be pre-computed for each source destination pair, and the network interface has a routing table to lookup the route.

Previously an integer of size 32-bit was inferred which is unnecessary loarge

…ing`

github-actions · 2024-02-25T10:22:38Z

hw/floo_axi_chimney.sv

    .RouteAlgo      ( RouteAlgo       ),
    .UseIdTable     ( UseIdTable      ),
    .XYAddrOffsetX  ( XYAddrOffsetX   ),
    .XYAddrOffsetY  ( XYAddrOffsetY   ),
    .IdAddrOffset   ( IdAddrOffset    ),
-    .NumRules       ( AddrMapNumRules ),
-    .AddrMap        ( AddrMap         ),
+    .NumAddrRules   ( SamNumRules     ),
+    .NumRoutes      ( NumRoutes       ),
    .id_t           ( id_t            ),
-    .id_rule_t      ( addr_map_rule_t ),
-    .addr_t         ( axi_in_addr_t   )
-  ) i_floo_narrow_route_comp [NumAddrDecoders-1:0] (
+    .addr_t         ( axi_in_addr_t   ),
+    .addr_rule_t    ( sam_rule_t      ),
+    .route_t        ( route_t         )
+  ) i_floo_req_route_comp [1:0] (
    .clk_i,
    .rst_ni,
-    .addr_i     ( addr_to_decode  ),
-    .id_o       ( decoded_id      )
+    .route_table_i,
+    .addr_map_i ( Sam                                     ),
+    .id_i       ( '0                                      ),
+    .addr_i     ( {axi_aw_queue.addr, axi_ar_queue.addr}  ),
+    .route_o    ( {route_out[AxiAw], route_out[AxiAr]}    ),
+    .id_o       ( {id_out[AxiAw], id_out[AxiAr]}          )
  );
-
-  assign dst_id[AxiAw] = decoded_id[AwReq];
-  assign dst_id[AxiW]  = axi_aw_id_q;
-  assign dst_id[AxiAr] = decoded_id[ArReq];
-  assign dst_id[AxiB]  = aw_out_data_out.src_id;
-  assign dst_id[AxiR]  = ar_out_data_out.src_id;
+  if (RouteAlgo == SourceRouting) begin : gen_route_field
+    floo_route_comp #(
+      .RouteAlgo    ( RouteAlgo     ),
+      .UseIdTable   ( 1'b0          ),
+      .NumAddrRules ( SamNumRules   ),
+      .NumRoutes    ( NumRoutes     ),
+      .id_t         ( id_t          ),
+      .addr_t       ( axi_in_addr_t ),
+      .addr_rule_t  ( sam_rule_t    ),
+      .route_t      ( route_t       )
+    ) i_floo_rsp_route_comp [1:0] (


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.RouteAlgo ( RouteAlgo ),

.UseIdTable ( UseIdTable ),

.XYAddrOffsetX ( XYAddrOffsetX ),

.XYAddrOffsetY ( XYAddrOffsetY ),

.IdAddrOffset ( IdAddrOffset ),

.NumRules ( AddrMapNumRules ),

.AddrMap ( AddrMap ),

.NumAddrRules ( SamNumRules ),

.NumRoutes ( NumRoutes ),

.id_t ( id_t ),

.id_rule_t ( addr_map_rule_t ),

.addr_t ( axi_in_addr_t )

) i_floo_narrow_route_comp [NumAddrDecoders-1:0] (

.addr_t ( axi_in_addr_t ),

.addr_rule_t ( sam_rule_t ),

.route_t ( route_t )

) i_floo_req_route_comp [1:0] (

.clk_i,

.rst_ni,

.addr_i ( addr_to_decode ),

.id_o ( decoded_id )

.route_table_i,

.addr_map_i ( Sam ),

.id_i ( '0 ),

.addr_i ( {axi_aw_queue.addr, axi_ar_queue.addr} ),

.route_o ( {route_out[AxiAw], route_out[AxiAr]} ),

.id_o ( {id_out[AxiAw], id_out[AxiAr]} )

);

assign dst_id[AxiAw] = decoded_id[AwReq];

assign dst_id[AxiW] = axi_aw_id_q;

assign dst_id[AxiAr] = decoded_id[ArReq];

assign dst_id[AxiB] = aw_out_data_out.src_id;

assign dst_id[AxiR] = ar_out_data_out.src_id;

if (RouteAlgo == SourceRouting) begin : gen_route_field

floo_route_comp #(

.RouteAlgo ( RouteAlgo ),

.UseIdTable ( 1'b0 ),

.NumAddrRules ( SamNumRules ),

.NumRoutes ( NumRoutes ),

.id_t ( id_t ),

.addr_t ( axi_in_addr_t ),

.addr_rule_t ( sam_rule_t ),

.route_t ( route_t )

) i_floo_rsp_route_comp [1:0] (

.RouteAlgo (RouteAlgo),

.UseIdTable (UseIdTable),

.XYAddrOffsetX(XYAddrOffsetX),

.XYAddrOffsetY(XYAddrOffsetY),

.IdAddrOffset (IdAddrOffset),

.NumAddrRules (SamNumRules),

.NumRoutes (NumRoutes),

.id_t (id_t),

.addr_t (axi_in_addr_t),

.addr_rule_t (sam_rule_t),

.route_t (route_t)

) i_floo_req_route_comp[1:0] (

github-actions · 2024-02-25T10:22:38Z

hw/floo_axi_chimney.sv

+      .addr_i     ( '0                                              ),
+      .addr_map_i ( '0                                              ),
+      .id_i       ({aw_out_data_out.src_id, ar_out_data_out.src_id} ),
+      .route_o    ({route_out[AxiB], route_out[AxiR]}               ),
+      .id_o       ({id_out[AxiB], id_out[AxiR]}                     )


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.addr_i ( '0 ),

.addr_map_i ( '0 ),

.id_i ({aw_out_data_out.src_id, ar_out_data_out.src_id} ),

.route_o ({route_out[AxiB], route_out[AxiR]} ),

.id_o ({id_out[AxiB], id_out[AxiR]} )

.addr_map_i(Sam),

.id_i ('0),

.addr_i ({axi_aw_queue.addr, axi_ar_queue.addr}),

.route_o ({route_out[AxiAw], route_out[AxiAr]}),

.id_o ({id_out[AxiAw], id_out[AxiAr]})

);

if (RouteAlgo == SourceRouting) begin : gen_route_field

floo_route_comp #(

.RouteAlgo (RouteAlgo),

.UseIdTable (1'b0),

.NumAddrRules(SamNumRules),

.NumRoutes (NumRoutes),

.id_t (id_t),

.addr_t (axi_in_addr_t),

.addr_rule_t (sam_rule_t),

.route_t (route_t)

) i_floo_rsp_route_comp[1:0] (

.clk_i,

.rst_ni,

.route_table_i,

.addr_i ('0),

.addr_map_i('0),

.id_i ({aw_out_data_out.src_id, ar_out_data_out.src_id}),

.route_o ({route_out[AxiB], route_out[AxiR]}),

.id_o ({id_out[AxiB], id_out[AxiR]})

github-actions · 2024-02-25T10:22:38Z

hw/floo_axi_chimney.sv

+    assign dst_id[AxiAw]  = id_out[AxiAw];
+    assign dst_id[AxiAr]  = id_out[AxiAr];
+    assign dst_id[AxiB]   = aw_out_data_out.src_id;
+    assign dst_id[AxiR]   = ar_out_data_out.src_id;
+    assign dst_id[AxiW]   = axi_aw_id_q;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign dst_id[AxiAw] = id_out[AxiAw];

assign dst_id[AxiAr] = id_out[AxiAr];

assign dst_id[AxiB] = aw_out_data_out.src_id;

assign dst_id[AxiR] = ar_out_data_out.src_id;

assign dst_id[AxiW] = axi_aw_id_q;

assign dst_id[AxiAw] = id_out[AxiAw];

assign dst_id[AxiAr] = id_out[AxiAr];

assign dst_id[AxiB] = aw_out_data_out.src_id;

assign dst_id[AxiR] = ar_out_data_out.src_id;

assign dst_id[AxiW] = axi_aw_id_q;

github-actions · 2024-02-25T10:22:38Z

hw/floo_axi_chimney.sv

  `FFL(axi_aw_id_q, dst_id[AxiAw], axi_aw_queue_valid_out &&
                                   axi_aw_queue_ready_in, '0)


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`FFL(axi_aw_id_q, dst_id[AxiAw], axi_aw_queue_valid_out &&

axi_aw_queue_ready_in, '0)

`FFL(axi_aw_id_q, dst_id[AxiAw], axi_aw_queue_valid_out && axi_aw_queue_ready_in, '0)

github-actions · 2024-02-25T10:22:38Z

hw/floo_narrow_wide_chimney.sv

    .RouteAlgo      ( RouteAlgo       ),
    .UseIdTable     ( UseIdTable      ),
    .XYAddrOffsetX  ( XYAddrOffsetX   ),
    .XYAddrOffsetY  ( XYAddrOffsetY   ),
    .IdAddrOffset   ( IdAddrOffset    ),
-    .NumRules       ( AddrMapNumRules ),
-    .AddrMap        ( AddrMap         ),
+    .NumAddrRules   ( SamNumRules     ),
+    .NumRoutes      ( NumRoutes       ),
    .id_t           ( id_t            ),
-    .id_rule_t      ( addr_map_rule_t ),
-    .addr_t         ( addr_t          )
-  ) i_floo_narrow_route_comp [NumAddrDecoders-1:0] (
+    .addr_t         ( addr_t          ),
+    .addr_rule_t    ( sam_rule_t      ),
+    .route_t        ( route_t         )
+  ) i_floo_req_route_comp [3:0] (
    .clk_i,
    .rst_ni,
-    .addr_i     ( addr_to_decode  ),
-    .id_o       ( decoded_id      )
+    .route_table_i,
+    .addr_map_i ( Sam ),
+    .id_i       ( '0  ),
+    .addr_i ({
+      axi_narrow_aw_queue.addr, axi_narrow_ar_queue.addr,
+      axi_wide_aw_queue.addr, axi_wide_ar_queue.addr
+    }),
+    .route_o  ({route_out[NarrowAw], route_out[NarrowAr], route_out[WideAw], route_out[WideAr]} ),
+    .id_o     ({id_out[NarrowAw], id_out[NarrowAr],id_out[WideAw], id_out[WideAr]}              )
  );

-  assign dst_id[NarrowAw] = decoded_id[NarrowAwReq];
-  assign dst_id[NarrowW]  = narrow_aw_id_q;
-  assign dst_id[NarrowAr] = decoded_id[NarrowArReq];
-  assign dst_id[NarrowB]  = narrow_aw_out_data_out.src_id;
-  assign dst_id[NarrowR]  = narrow_ar_out_data_out.src_id;
-  assign dst_id[WideAw] = decoded_id[WideAwReq];
-  assign dst_id[WideW]  = wide_aw_id_q;
-  assign dst_id[WideAr] = decoded_id[WideArReq];
-  assign dst_id[WideB]  = wide_aw_out_data_out.src_id;
-  assign dst_id[WideR]  = wide_ar_out_data_out.src_id;
+  if (RouteAlgo == SourceRouting) begin : gen_route_field
+    floo_route_comp #(
+      .RouteAlgo    ( RouteAlgo   ),
+      .UseIdTable   ( 1'b0        ),
+      .NumAddrRules ( SamNumRules ),
+      .NumRoutes    ( NumRoutes   ),
+      .id_t         ( id_t        ),
+      .addr_t       ( addr_t      ),
+      .addr_rule_t  ( sam_rule_t  ),
+      .route_t      ( route_t     )
+      ) i_floo_rsp_route_comp [3:0] (


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.RouteAlgo ( RouteAlgo ),

.UseIdTable ( UseIdTable ),

.XYAddrOffsetX ( XYAddrOffsetX ),

.XYAddrOffsetY ( XYAddrOffsetY ),

.IdAddrOffset ( IdAddrOffset ),

.NumRules ( AddrMapNumRules ),

.AddrMap ( AddrMap ),

.NumAddrRules ( SamNumRules ),

.NumRoutes ( NumRoutes ),

.id_t ( id_t ),

.id_rule_t ( addr_map_rule_t ),

.addr_t ( addr_t )

) i_floo_narrow_route_comp [NumAddrDecoders-1:0] (

.addr_t ( addr_t ),

.addr_rule_t ( sam_rule_t ),

.route_t ( route_t )

) i_floo_req_route_comp [3:0] (

.clk_i,

.rst_ni,

.addr_i ( addr_to_decode ),

.id_o ( decoded_id )

.route_table_i,

.addr_map_i ( Sam ),

.id_i ( '0 ),

.addr_i ({

axi_narrow_aw_queue.addr, axi_narrow_ar_queue.addr,

axi_wide_aw_queue.addr, axi_wide_ar_queue.addr

}),

.route_o ({route_out[NarrowAw], route_out[NarrowAr], route_out[WideAw], route_out[WideAr]} ),

.id_o ({id_out[NarrowAw], id_out[NarrowAr],id_out[WideAw], id_out[WideAr]} )

);

assign dst_id[NarrowAw] = decoded_id[NarrowAwReq];

assign dst_id[NarrowW] = narrow_aw_id_q;

assign dst_id[NarrowAr] = decoded_id[NarrowArReq];

assign dst_id[NarrowB] = narrow_aw_out_data_out.src_id;

assign dst_id[NarrowR] = narrow_ar_out_data_out.src_id;

assign dst_id[WideAw] = decoded_id[WideAwReq];

assign dst_id[WideW] = wide_aw_id_q;

assign dst_id[WideAr] = decoded_id[WideArReq];

assign dst_id[WideB] = wide_aw_out_data_out.src_id;

assign dst_id[WideR] = wide_ar_out_data_out.src_id;

if (RouteAlgo == SourceRouting) begin : gen_route_field

floo_route_comp #(

.RouteAlgo ( RouteAlgo ),

.UseIdTable ( 1'b0 ),

.NumAddrRules ( SamNumRules ),

.NumRoutes ( NumRoutes ),

.id_t ( id_t ),

.addr_t ( addr_t ),

.addr_rule_t ( sam_rule_t ),

.route_t ( route_t )

) i_floo_rsp_route_comp [3:0] (

.RouteAlgo (RouteAlgo),

.UseIdTable (UseIdTable),

.XYAddrOffsetX(XYAddrOffsetX),

.XYAddrOffsetY(XYAddrOffsetY),

.IdAddrOffset (IdAddrOffset),

.NumAddrRules (SamNumRules),

.NumRoutes (NumRoutes),

.id_t (id_t),

.addr_t (addr_t),

.addr_rule_t (sam_rule_t),

.route_t (route_t)

) i_floo_req_route_comp[3:0] (

github-actions · 2024-02-25T10:22:39Z

hw/floo_route_comp.sv

  end else begin : gen_error
    $fatal(1, "Routing algorithm not implemented");
  end
+  if (RouteAlgo == SourceRouting) begin : gen_route
+    assign route_o = (UseIdTable)? route_table_i[id_o] : route_table_i[id_i];


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign route_o = (UseIdTable)? route_table_i[id_o] : route_table_i[id_i];

assign route_o = (UseIdTable) ? route_table_i[id_o] : route_table_i[id_i];

github-actions · 2024-02-25T10:22:39Z

hw/tb/tb_floo_dma_chimney.sv

    .AtopSupport        ( 1'b0                ),
-    .RouteAlgo          ( floo_pkg::IdTable   ),
    .MaxTxns            ( MaxTxns             ),
    .MaxTxnsPerId       ( MaxTxnsPerId        ),
    .ReorderBufferSize  ( ReorderBufferSize   )


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.AtopSupport ( 1'b0 ),

.RouteAlgo ( floo_pkg::IdTable ),

.MaxTxns ( MaxTxns ),

.MaxTxnsPerId ( MaxTxnsPerId ),

.ReorderBufferSize ( ReorderBufferSize )

.AtopSupport (1'b0),

.MaxTxns (MaxTxns),

.MaxTxnsPerId (MaxTxnsPerId),

.ReorderBufferSize(ReorderBufferSize)

github-actions · 2024-02-25T10:22:39Z

hw/tb/tb_floo_dma_chimney.sv

    .AtopSupport        ( 1'b0                ),
-    .RouteAlgo          ( floo_pkg::IdTable   ),
    .MaxTxns            ( MaxTxns             ),
    .MaxTxnsPerId       ( MaxTxnsPerId        ),
    .ReorderBufferSize  ( ReorderBufferSize   )


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.AtopSupport ( 1'b0 ),

.RouteAlgo ( floo_pkg::IdTable ),

.MaxTxns ( MaxTxns ),

.MaxTxnsPerId ( MaxTxnsPerId ),

.ReorderBufferSize ( ReorderBufferSize )

.AtopSupport (1'b0),

.MaxTxns (MaxTxns),

.MaxTxnsPerId (MaxTxnsPerId),

.ReorderBufferSize(ReorderBufferSize)

github-actions · 2024-02-25T10:22:39Z

hw/tb/tb_floo_dma_mesh.sv

@@ -24,9 +24,13 @@ module tb_floo_dma_mesh;
  localparam axi_narrow_in_addr_t HBMSize = 48'h10000; // 64KB


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

localparam axi_narrow_in_addr_t HBMSize = 48'h10000; // 64KB

localparam axi_narrow_in_addr_t HBMSize = 48'h10000; // 64KB

github-actions · 2024-02-25T10:22:40Z

hw/tb/tb_floo_dma_mesh.sv

  `ASSERT_INIT(NotEnoughXBits, $clog2(NumX + 2) <= $bits(x_bits_t))
  `ASSERT_INIT(NotEnoughYBits, $clog2(NumY + 2) <= $bits(y_bits_t))
  `ASSERT_INIT(NotEnoughAddrOffset, $clog2(HBMSize) <= XYAddrOffsetX)


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`ASSERT_INIT(NotEnoughXBits, $clog2(NumX + 2) <= $bits(x_bits_t))

`ASSERT_INIT(NotEnoughYBits, $clog2(NumY + 2) <= $bits(y_bits_t))

`ASSERT_INIT(NotEnoughAddrOffset, $clog2(HBMSize) <= XYAddrOffsetX)

`ASSERT_INIT(NotEnoughXBits, $clog2(NumX + 2) <= $bits(x_bits_t))

`ASSERT_INIT(NotEnoughYBits, $clog2(NumY + 2) <= $bits(y_bits_t))

`ASSERT_INIT(NotEnoughAddrOffset, $clog2(HBMSize) <= XYAddrOffsetX)

* hw(pkg): Rename `Consumption` routing to `SourceRouting` * hw(router): Implement `SourceRouting` by consumption * hw(chimney): Implement `SourceRouting` * tb: Add new `map_i` port to all chimneys * pkg: Define axi_ch enum with specific number of bits Previously an integer of size 32-bit was inferred which is unnecessary loarge * hw(routing): Support both table & address map * hw(chimney): Compute route for response packet in case of `SourceRouting` * pkg: Define the preliminary output type of the route computation * floogen(endpoint): Add additional helper functions * floogen(routing): Enable sorting by endpoint ID * floogen(routing): Add source-based routing algorithm * floogen(tpl): Adapt templates * hw(routing): Use two-stage address decoding for source-based routing * hw(chimney): Adapt to support source-based routing * floogen(test): Refactoring * floogen(utils): Modify helper functions * hw(tb): Refactor port of chimneys * floogen(examples): Add mesh example with source-based routing * hw(pkg): Regenerate package sources * floogen(test): Fix unit tests * hw(chimney): Fix multiple-driven assignments * floogen: Linting * hw(chimney): Linting * floogen: Small fix * hw(pkg): Set number of address rules to 1 by default * hw(routing): Fix address translation bug * hw(chimney): Give `route_comp` modules a proper name * floogen(tpl): Fix chimney ports * floogen(routing): Fix bit width of XY coordinates * floogen(tpl): Small fixes in templates * floogen(routing): Render the route table in reverse * doc: Update CHANGELOG * tb: Fix compilation errors with routing algorithms * lint: Make linter happy

fischeti added 30 commits February 12, 2024 16:39

hw(pkg): Rename Consumption routing to SourceRouting

01b9b9f

hw(router): Implement SourceRouting by consumption

1e07698

hw(chimney): Implement SourceRouting

2c97992

tb: Add new map_i port to all chimneys

c21aab7

pkg: Define axi_ch enum with specific number of bits

0386972

Previously an integer of size 32-bit was inferred which is unnecessary loarge

hw(routing): Support both table & address map

76ceebe

hw(chimney): Compute route for response packet in case of `SourceRout…

4e19eec

…ing`

pkg: Define the preliminary output type of the route computation

102fc6d

floogen(endpoint): Add additional helper functions

3113395

floogen(routing): Enable sorting by endpoint ID

96f6a15

floogen(routing): Add source-based routing algorithm

c0ebdbe

floogen(tpl): Adapt templates

820d1e7

hw(routing): Use two-stage address decoding for source-based routing

ade8579

hw(chimney): Adapt to support source-based routing

ffe0e83

floogen(test): Refactoring

6a7bc8b

floogen(utils): Modify helper functions

194f5cc

hw(tb): Refactor port of chimneys

808016d

floogen(examples): Add mesh example with source-based routing

44167e2

hw(pkg): Regenerate package sources

0b6f1ce

floogen(test): Fix unit tests

18959aa

hw(chimney): Fix multiple-driven assignments

2b8d6e5

floogen: Linting

4ef6e79

hw(chimney): Linting

8571674

floogen: Small fix

6c76c0c

hw(pkg): Set number of address rules to 1 by default

b1c24d5

hw(routing): Fix address translation bug

0e07ca0

hw(chimney): Give route_comp modules a proper name

86d5710

floogen(tpl): Fix chimney ports

449d58a

floogen(routing): Fix bit width of XY coordinates

34a8180

floogen(tpl): Small fixes in templates

ba673fd

fischeti added 4 commits February 15, 2024 18:19

floogen(routing): Render the route table in reverse

394b051

doc: Update CHANGELOG

109bf6c

tb: Fix compilation errors with routing algorithms

67fd4af

lint: Make linter happy

ff2e098

github-actions bot reviewed Feb 25, 2024

View reviewed changes

fischeti merged commit e1c846d into main Feb 25, 2024
25 checks passed

fischeti deleted the source-routing branch February 25, 2024 10:23

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routing: Add source-based routing algorithm #30

routing: Add source-based routing algorithm #30

fischeti commented Feb 25, 2024

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-      .addr_i     ( '0                                              ),
-      .addr_map_i ( '0                                              ),
-      .id_i       ({aw_out_data_out.src_id, ar_out_data_out.src_id} ),
-      .route_o    ({route_out[AxiB], route_out[AxiR]}               ),
-      .id_o       ({id_out[AxiB], id_out[AxiR]}                     )
+      .addr_map_i(Sam),
+      .id_i      ('0),
+      .addr_i    ({axi_aw_queue.addr, axi_ar_queue.addr}),
+      .route_o   ({route_out[AxiAw], route_out[AxiAr]}),
+      .id_o      ({id_out[AxiAw], id_out[AxiAr]})
+  );
+  if (RouteAlgo == SourceRouting) begin : gen_route_field
+    floo_route_comp #(
+        .RouteAlgo   (RouteAlgo),
+        .UseIdTable  (1'b0),
+        .NumAddrRules(SamNumRules),
+        .NumRoutes   (NumRoutes),
+        .id_t        (id_t),
+        .addr_t      (axi_in_addr_t),
+        .addr_rule_t (sam_rule_t),
+        .route_t     (route_t)
+    ) i_floo_rsp_route_comp[1:0] (
+        .clk_i,
+        .rst_ni,
+        .route_table_i,
+        .addr_i    ('0),
+        .addr_map_i('0),
+        .id_i      ({aw_out_data_out.src_id, ar_out_data_out.src_id}),
+        .route_o   ({route_out[AxiB], route_out[AxiR]}),
+        .id_o      ({id_out[AxiB], id_out[AxiR]})

		`FFL(axi_aw_id_q, dst_id[AxiAw], axi_aw_queue_valid_out &&
		axi_aw_queue_ready_in, '0)

	assign route_o = (UseIdTable)? route_table_i[id_o] : route_table_i[id_i];
	assign route_o = (UseIdTable) ? route_table_i[id_o] : route_table_i[id_i];

		@@ -24,9 +24,13 @@ module tb_floo_dma_mesh;
		localparam axi_narrow_in_addr_t HBMSize = 48'h10000; // 64KB

routing: Add source-based routing algorithm #30

routing: Add source-based routing algorithm #30

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