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hw: Minor fix for verilator compilation #49

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merged 3 commits into from
Jun 24, 2024
Merged

hw: Minor fix for verilator compilation #49

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49650f2
hw(vc_arbiter): Fix typedef when using no virtual channels
fischeti Jun 24, 2024
774d12f
doc: Update CHANGELOG
fischeti Jun 24, 2024
fb5f833
make: Don't use pkg sources as prerequisite
fischeti Jun 24, 2024
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -23,6 +23,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
- Broadcasted input `id_i` in the chimneys should not throw an error anymore in elaboration.
- The `id_offset` should not be correctly applied in the system address map. Before it resulted in negative coordinates.
- The `axi_ch_e` types now have an explicit bitwidth. Previously, this caused issues during elaboration since a 32-bit integer was used as a type.
- Fixed a typedef in `floo_vc_arbiter` when setting `NumVirtChannels` to 1, that caused issue when compiling with Verilator.

### Removed

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2 changes: 1 addition & 1 deletion Makefile
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Expand Up @@ -126,7 +126,7 @@ scripts/compile_vsim.tcl: Bender.yml
$(BENDER) script vsim --vlog-arg="$(VLOG_ARGS)" $(BENDER_FLAGS) | grep -v "set ROOT" >> scripts/compile_vsim.tcl
echo >> scripts/compile_vsim.tcl

compile-sim: scripts/compile_vsim.tcl $(FLOOGEN_PKG_SRC)
compile-sim: scripts/compile_vsim.tcl
$(VSIM) -64 -c -do "source scripts/compile_vsim.tcl; quit"

run-sim:
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13 changes: 6 additions & 7 deletions hw/floo_vc_arbiter.sv
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Expand Up @@ -11,7 +11,7 @@
parameter type flit_t = logic,
parameter int unsigned NumPhysChannels = 1
) (
input logic clk_i,

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[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
hw/floo_vc_arbiter.sv:14:-  input  logic                        clk_i,
hw/floo_vc_arbiter.sv:15:-  input  logic                        rst_ni,
hw/floo_vc_arbiter.sv:16:-  /// Ports towards the virtual channels
hw/floo_vc_arbiter.sv:17:-  input  logic  [NumVirtChannels-1:0] valid_i,
hw/floo_vc_arbiter.sv:18:-  output logic  [NumVirtChannels-1:0] ready_o,
hw/floo_vc_arbiter.sv:19:-  input  flit_t [NumVirtChannels-1:0] data_i,
hw/floo_vc_arbiter.sv:20:-  /// Ports towards the physical channels
hw/floo_vc_arbiter.sv:21:-  input  logic  [NumVirtChannels-1:0] ready_i,
hw/floo_vc_arbiter.sv:22:-  output logic  [NumVirtChannels-1:0] valid_o,
hw/floo_vc_arbiter.sv:23:-  output flit_t [NumPhysChannels-1:0] data_o
hw/floo_vc_arbiter.sv:15:+    input  logic                        clk_i,
hw/floo_vc_arbiter.sv:16:+    input  logic                        rst_ni,
hw/floo_vc_arbiter.sv:17:+    /// Ports towards the virtual channels
hw/floo_vc_arbiter.sv:18:+    input  logic  [NumVirtChannels-1:0] valid_i,
hw/floo_vc_arbiter.sv:19:+    output logic  [NumVirtChannels-1:0] ready_o,
hw/floo_vc_arbiter.sv:20:+    input  flit_t [NumVirtChannels-1:0] data_i,
hw/floo_vc_arbiter.sv:21:+    /// Ports towards the physical channels
hw/floo_vc_arbiter.sv:22:+    input  logic  [NumVirtChannels-1:0] ready_i,
hw/floo_vc_arbiter.sv:23:+    output logic  [NumVirtChannels-1:0] valid_o,
hw/floo_vc_arbiter.sv:24:+    output flit_t [NumPhysChannels-1:0] data_o

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[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
hw/floo_vc_arbiter.sv:14:-  input  logic                        clk_i,
hw/floo_vc_arbiter.sv:15:-  input  logic                        rst_ni,
hw/floo_vc_arbiter.sv:16:-  /// Ports towards the virtual channels
hw/floo_vc_arbiter.sv:17:-  input  logic  [NumVirtChannels-1:0] valid_i,
hw/floo_vc_arbiter.sv:18:-  output logic  [NumVirtChannels-1:0] ready_o,
hw/floo_vc_arbiter.sv:19:-  input  flit_t [NumVirtChannels-1:0] data_i,
hw/floo_vc_arbiter.sv:20:-  /// Ports towards the physical channels
hw/floo_vc_arbiter.sv:21:-  input  logic  [NumVirtChannels-1:0] ready_i,
hw/floo_vc_arbiter.sv:22:-  output logic  [NumVirtChannels-1:0] valid_o,
hw/floo_vc_arbiter.sv:23:-  output flit_t [NumPhysChannels-1:0] data_o
hw/floo_vc_arbiter.sv:15:+    input  logic                        clk_i,
hw/floo_vc_arbiter.sv:16:+    input  logic                        rst_ni,
hw/floo_vc_arbiter.sv:17:+    /// Ports towards the virtual channels
hw/floo_vc_arbiter.sv:18:+    input  logic  [NumVirtChannels-1:0] valid_i,
hw/floo_vc_arbiter.sv:19:+    output logic  [NumVirtChannels-1:0] ready_o,
hw/floo_vc_arbiter.sv:20:+    input  flit_t [NumVirtChannels-1:0] data_i,
hw/floo_vc_arbiter.sv:21:+    /// Ports towards the physical channels
hw/floo_vc_arbiter.sv:22:+    input  logic  [NumVirtChannels-1:0] ready_i,
hw/floo_vc_arbiter.sv:23:+    output logic  [NumVirtChannels-1:0] valid_o,
hw/floo_vc_arbiter.sv:24:+    output flit_t [NumPhysChannels-1:0] data_o
input logic rst_ni,
/// Ports towards the virtual channels
input logic [NumVirtChannels-1:0] valid_i,
Expand All @@ -23,14 +23,13 @@
output flit_t [NumPhysChannels-1:0] data_o
);

typedef logic [$clog2(NumVirtChannels)-1:0] arb_idx_t;

if (NumVirtChannels == NumPhysChannels) begin : gen_virt_eq_phys
assign valid_o = valid_i;
assign ready_o = ready_i;
assign data_o = data_i;
end else if (NumPhysChannels == 1) begin : gen_single_phys
if (NumVirtChannels == NumPhysChannels) begin : gen_virt_eq_phys
assign valid_o = valid_i;
assign ready_o = ready_i;
assign data_o = data_i;
end else if (NumPhysChannels == 1) begin : gen_single_phys
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
if (NumVirtChannels == NumPhysChannels) begin : gen_virt_eq_phys
assign valid_o = valid_i;
assign ready_o = ready_i;
assign data_o = data_i;
end else if (NumPhysChannels == 1) begin : gen_single_phys
if (NumVirtChannels == NumPhysChannels) begin : gen_virt_eq_phys
assign valid_o = valid_i;
assign ready_o = ready_i;
assign data_o = data_i;
end else if (NumPhysChannels == 1) begin : gen_single_phys


typedef logic [$clog2(NumVirtChannels)-1:0] arb_idx_t;
arb_idx_t vc_arb_idx;

logic [NumVirtChannels-1:0] vc_arb_req_in;
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