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treewide: Preparation for v1.0.0, add SV macros for type definitions and refactor module parametrization #65

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Sep 17, 2024
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1d801a0
hw(simple_rob): Add assertions that `floo_simple_rob` which does not …
fischeti Sep 10, 2024
290d7a7
hw(rob): Use per-ID offset counter
fischeti Sep 10, 2024
4651a4a
treewide: Introduce macros and remove generated types
fischeti Sep 3, 2024
96f5538
floogen(examples): Remove pkg-only configurations
fischeti Sep 11, 2024
280d79d
sim(waves): Remove/Rename wave scripts
fischeti Sep 11, 2024
2f95e94
hw(param): Rename `SamNumRules` to `NumSamRules`
fischeti Sep 13, 2024
23696da
hw(utils): Add helper function to render SV struct assignments
fischeti Sep 13, 2024
784fffa
hw(typedef): Clean up typedef include file
fischeti Sep 13, 2024
83222d2
hw(templates): Rename file names for better consistency
fischeti Sep 13, 2024
bf63066
hw(param): Remove redundant `NumAddrRules`
fischeti Sep 13, 2024
aaa5128
hw(pkg): Add helper function to enable manager/subordinate ports
fischeti Sep 13, 2024
2e1d014
floogen(routing): Render new hdr and route cfg
fischeti Sep 13, 2024
0cf8a4f
floogen(link): Render links with new typedefs
fischeti Sep 13, 2024
11958ed
floogen(network): Check matching address and user width
fischeti Sep 13, 2024
6277152
floogen(protocol): Make it possible to render ports with pkg prefix
fischeti Sep 13, 2024
1d9c73e
floogen(routing): Store NI routing table in `routing` field
fischeti Sep 13, 2024
ce6efe0
floogen(protocol): Adapt protocol information input and rendering
fischeti Sep 13, 2024
c1facbc
floogen(cli): Remove deprecated package rendering
fischeti Sep 13, 2024
576b6b3
floogen(examples): Adapt examples to new configuration file schema
fischeti Sep 13, 2024
c5b9765
floogen: Linting
fischeti Sep 13, 2024
c08c5ec
ci: Make CI fail on compilation errors
fischeti Sep 13, 2024
969e47d
hw(vc_chimney): Use `NumAddrRules` parameter
fischeti Sep 13, 2024
4aa4084
ci: Use correct file names of generated NoCs
fischeti Sep 13, 2024
1655bbb
hw(routing): Remove `IdIsPort` Routing Algorithm
fischeti Sep 13, 2024
3567bbf
hw(rob): Remove unused `MaxRoTxnsPerId` parameter from `floo_simple_rob`
fischeti Sep 13, 2024
f915643
hw(docs): Add documentation in the form of comments
fischeti Sep 13, 2024
e68a47f
hw(rob): Rename `RoBDepth` to `RoBSize`
fischeti Sep 13, 2024
8476d8c
docs: Update CHANGELOG
fischeti Sep 13, 2024
bed66f2
hw(pkg): Remove `floo_narrow_wide_pkg`
fischeti Sep 13, 2024
e9ea327
floogen(tpl): Include `axi` typedefs
fischeti Sep 13, 2024
33a7bed
floogen(tpl): Include `floo_noc` typedefs
fischeti Sep 13, 2024
647dfc8
floogen(tpl): Fix type parameters of `nw_chimney`
fischeti Sep 13, 2024
e46a54c
hw(chimney): Pass ID widths to meta buffer
fischeti Sep 13, 2024
085b7d6
floogen(cfg): Disallow extra members for typos
fischeti Sep 17, 2024
14aa001
floogen(chimney): Use `table` instead of `routing.table` for source-b…
fischeti Sep 17, 2024
39d543d
floogen(routing): Fix number of routes
fischeti Sep 17, 2024
6cf72c7
floogen(tpl): Also define types for degenerate ports
fischeti Sep 17, 2024
09cc187
hw(chimney): Parametrize `dst_t` which can be either `id_t` or `route_t`
fischeti Sep 17, 2024
f226ac7
floogen(tpl): Pass `dst_t` parameter for source-based routing
fischeti Sep 17, 2024
502ed29
hw(topologies): Remove obsolete `mesh` and `ruche_mesh` modules
fischeti Sep 17, 2024
21df1d2
hw(router): Whitespace changes
fischeti Sep 17, 2024
2bba413
docs: Remove topologies from README
fischeti Sep 17, 2024
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2 changes: 1 addition & 1 deletion .github/workflows/floogen.yml
Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,7 @@ jobs:
uses: actions/upload-artifact@v4
with:
name: ${{ matrix.examples }}
path: generated/${{ matrix.examples }}_floo_noc.sv
path: generated/floo_${{ matrix.examples }}_noc.sv
if-no-files-found: error
retention-days: 1

Expand Down
56 changes: 0 additions & 56 deletions .github/workflows/lint.yml
Original file line number Diff line number Diff line change
Expand Up @@ -14,62 +14,6 @@ on:

jobs:

###############
# Check Clean #
###############
check-clean:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v4
- uses: actions/setup-python@v5
with:
python-version: '3.10'
cache: 'pip'
- name: Install dependencies and package
run: |
python -m pip install --upgrade pip
pip install .
- name: Install bender
uses: pulp-platform/pulp-actions/bender-install@v2
- name: Install Verible
uses: chipsalliance/verible-actions-common/install-verible@main
with:
github_token: ${{ secrets.GITHUB_TOKEN }}
- name: Make clean sources
run: |
make clean pkg-sources
- name: Check clean
run: |
git status && test -z "$(git status --porcelain)"

###############
# Check Stale #
###############
check-stale:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v4
- uses: actions/setup-python@v5
with:
python-version: '3.10'
cache: 'pip'
- name: Install dependencies and package
run: |
python -m pip install --upgrade pip
pip install .
- name: Install bender
uses: pulp-platform/pulp-actions/bender-install@v2
- name: Install Verible
uses: chipsalliance/verible-actions-common/install-verible@main
with:
github_token: ${{ secrets.GITHUB_TOKEN }}
- name: Make clean sources
run: |
make -B pkg-sources
- name: Check clean
run: |
git status && test -z "$(git status --porcelain)"

#####################
# Bender up-to-date #
#####################
Expand Down
6 changes: 3 additions & 3 deletions .gitlab-ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@ compile-vsim:
stage: build
script:
- make compile-sim VC=true | tee compile.log 2>&1
- '! grep "Error: " compile.log'
- '! grep "\*\* Error" compile.log'
needs:
- collect-bender-sources
artifacts:
Expand All @@ -49,7 +49,7 @@ run-vsim:
- tb_floo_router
- tb_floo_vc_router
- tb_floo_axi_chimney
- tb_floo_narrow_wide_chimney
- tb_floo_nw_chimney
- tb_floo_rob
needs:
- collect-bender-sources
Expand All @@ -65,7 +65,7 @@ run-traffic:
JOB_NAME: mesh
parallel:
matrix:
- VSIM_TB_DUT: [tb_floo_dma_mesh, tb_floo_vc_dma_mesh]
- VSIM_TB_DUT: [tb_floo_dma_mesh] # Fix: `tb_floo_vc_dma_mesh` has issues with boundary accesses
TRAFFIC_TYPE: [random, hbm, onehop, bit_complement, bit_reverse, bit_rotation, neighbor, shuffle, transpose, tornado, single_dest_boundary, single_dest_center]
TRAFFIC_RW: [read, write]
needs:
Expand Down
18 changes: 6 additions & 12 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -21,8 +21,6 @@ export_include_dirs:
sources:
# Level 0
- hw/floo_pkg.sv
- hw/floo_axi_pkg.sv
- hw/floo_narrow_wide_pkg.sv
# Level 1
- hw/floo_cut.sv
- hw/floo_fifo.sv
Expand All @@ -36,11 +34,11 @@ sources:
- hw/floo_rob_wrapper.sv
- hw/floo_meta_buffer.sv
# Level 2
- hw/floo_narrow_wide_join.sv
- hw/floo_nw_join.sv
- hw/floo_axi_chimney.sv
- hw/floo_narrow_wide_chimney.sv
- hw/floo_nw_chimney.sv
- hw/floo_router.sv
- hw/floo_narrow_wide_router.sv
- hw/floo_nw_router.sv

- target: vc_router
files:
Expand All @@ -56,12 +54,10 @@ sources:
- hw/vc_router_util/floo_vc_assignment.sv
- hw/vc_router_util/floo_vc_router_switch.sv
- hw/vc_router_util/floo_vc_selection.sv
- hw/floo_vc_axi_pkg.sv
- hw/floo_vc_narrow_wide_pkg.sv
# Level 2
- hw/floo_vc_narrow_wide_chimney.sv
- hw/floo_vc_router.sv
- hw/floo_vc_narrow_wide_router.sv
- hw/floo_nw_vc_chimney.sv
- hw/floo_nw_vc_router.sv

- target: test
include_dirs:
Expand All @@ -79,11 +75,9 @@ sources:
- hw/test/floo_hbm_model.sv
# Level 2
- hw/tb/tb_floo_axi_chimney.sv
- hw/tb/tb_floo_narrow_wide_chimney.sv
- hw/tb/tb_floo_nw_chimney.sv
- hw/tb/tb_floo_router.sv
- hw/tb/tb_floo_rob.sv
- hw/tb/tb_floo_dma_chimney.sv
- hw/tb/tb_floo_dma_nw_chimney.sv
- hw/tb/tb_floo_dma_mesh.sv

- target: all(test, vc_router)
Expand Down
55 changes: 55 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,61 @@ All notable changes to this project will be documented in this file.

The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).

## Unreleased

### Added

#### Hardware
- The `floo_pkg` was extended with helper functions to calculate the size of AXI payloads and mapping of AXI to Floo Channels.
- Multiple configuration structs were introduced to enable a more flexible and non-verbose configuration of the FlooNoC modules.
- The `AxiCfg` describes all the necessary parameters needed for the type definitions of a bidirectional AXI interface
- The `RouteCfg` describes all the necessary routing information parameters required by the chimneys.
- The `ChimneyCfg` describes all other parameters for the data path of the chimney (e.g. Mgr/Sbr port enable, number of oustanding transactions, RoB types & sizes, etc.)
- The `floo_test_pkg` now defines default configurations for all the new configuration structs that are used by the testbenches.

#### FlooGen
- The `data_width` and `user_width` fields for `protocols` are now also validated to be compatible with each other.
- All the various `*Cfg`'s is now rendered by _FlooGen_, either in the `*_noc_pkg` or in the `*_noc` module itself.

### Changed

#### Hardware
- The `floo_narrow_wide_*` modules and the corresponding testbenches were renamed to `floo_nw_*` to be more concise.
- The flit type definitions are now implemented as SystemVerilog macros in `typedef.svh`.
- The parametrization of the chimney modules has changed dramatically. They now use the newly introduced `*Cfg`'s from the `floo_pkg`. In the narrow-wide chimneys, both datapaths now have their own configs (i.e. `*CfgN` and `*CfgW`), to reduce the verbosity of the module instantiation.
- The payload field name in each `*_chan_t` type previously had its own name. This was unified to `payload` since `*_chan_t` already determines the type of the payload.
- The input and output buffer FIFO depth of the routers were renamed to `InFifoDepth` and `OutFifoDepth` to be more consistent (previously `ChannelFifoDepth` and `OutputFifoDepth`).
- The narrow-wide router wrapper now also requires the `AxiCfg` structs to redefine the link types internally.
- The `ReorderBufferSize` parameters was shortened to `RoBSize`.
- All testbenches were adapted to all changes.
- All verification IPs were adapted to the new configuration structs.

#### FlooGen
- The link typedefs are now renderd with the macros in `typedef.svh` instead of rendering them in pure SystemVerilog.
- The template files were renamed to use the more concise `nw` naming scheme.
- The generated modules and packages of _FlooGen_ are now named `floo_*_noc` resp. `floo_*_noc_pkg` which is more consistent since all other modules have the `floo_*` prefix.
- The `protocols` schema was adapted a bit to be more intuitive.
- The `type` field was renamed to `protocol`, which currently only accepts `AXI4`. A new `type` field now is used by _FlooGen_ to now where to attach the protocol in the network interface. Currently, _FlooGen_ only supports the narrow-wide AXI configuration, hence only `narrow|wide` is allowed as `type` values.
- The `direction` field in the `protocol` schema is no longer required, since the direction is determined when specifying `mgr_port_protocol` and `sbr_port_protocol`.
- The `name` field must be unique now, since it is used by `mgr_port_protocol` and `sbr_port_protocol` to reference the exact protocol.
- All examples were adapted to reflect those changes.

### Fixed

- A bug in the calcuation of the RoB offset in `floo_rob` was fixed. Previously, the allocation and the write process used the same counter in bursts for offset calculation, which resulted in wrong offsets.

### Removed

#### Hardware

- As the flit type definitions were moved to `typedef.svh`, the auto-generated `floo_*_pkg` packages were removed from the repository. Furthermore, all the (global) imports of those packages in the modules were replaced by parameters.
- The testbench `tb_floo_nw_chimney` was removed since it was neither used nor maintained anymore.
- The `IdIsPort` routing algorithm was removed since it can only be used for routes over a single router. The same functionality can be achieved with the `SourceRouting` algorithm.

#### FlooGen
- The package generation was removed from _FlooGen_ since it is now handled by the `typedef.svh` file. Further, the `--only-pkg` and `--pkg-outdir` flags were removed from the _FlooGen_ CLI.
- The calculation of link sizes and AXI to Floo channel mapping was removed from the _FlooGen_ configuration file. This is now handled by the `floo_pkg` helper functions.

## [0.5.0] - 2024-09-13

### Added
Expand Down
15 changes: 3 additions & 12 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -72,15 +72,10 @@ endif
###########

FLOOGEN ?= floogen
FLOO_CFG_DIR ?= $(MKFILE_DIR)floogen/examples
FLOOGEN_CFG ?= $(FLOO_CFG_DIR)/single_cluster.yml

FLOOGEN_OUT_DIR ?= $(MKFILE_DIR)generated
FLOOGEN_PKG_OUT_DIR ?= $(MKFILE_DIR)hw
FLOOGEN_CFG_DIR ?= $(MKFILE_DIR)floogen/examples
FLOOGEN_TPL_DIR ?= $(MKFILE_DIR)floogen/templates

FLOOGEN_PKG_CFG ?= $(shell find $(FLOOGEN_CFG_DIR) -name "*_pkg.yml")
FLOOGEN_PKG_SRC ?= $(patsubst $(FLOOGEN_CFG_DIR)/%_pkg.yml,$(FLOOGEN_PKG_OUT_DIR)/floo_%_pkg.sv,$(FLOOGEN_PKG_CFG))
FLOOGEN_TPL ?= $(shell find $(FLOOGEN_TPL_DIR) -name "*.mako")

.PHONY: install-floogen pkg-sources sources clean-sources

Expand All @@ -90,12 +85,8 @@ check-floogen:
install-floogen:
@which $(FLOOGEN) > /dev/null || (echo "Installing floogen..." && pip install .)

pkg-sources: check-floogen $(FLOOGEN_PKG_SRC)
$(FLOOGEN_PKG_OUT_DIR)/floo_%_pkg.sv: $(FLOOGEN_CFG_DIR)/%_pkg.yml $(FLOOGEN_TPL)
$(FLOOGEN) -c $< --only-pkg --pkg-outdir $(FLOOGEN_PKG_OUT_DIR) $(FLOOGEN_ARGS)

sources: check-floogen
$(FLOOGEN) -c $(FLOOGEN_CFG) -o $(FLOOGEN_OUT_DIR) --pkg-outdir $(FLOOGEN_PKG_OUT_DIR) $(FLOOGEN_ARGS)
$(FLOOGEN) -c $(FLOOGEN_CFG) -o $(FLOOGEN_OUT_DIR) $(FLOOGEN_ARGS)

clean-sources:
rm -rf $(FLOOGEN_OUT_DIR)
Expand Down
13 changes: 3 additions & 10 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -96,10 +96,9 @@ This repository includes the following NoC IPs:

1. **Routers:** A collection of different NoC router designs with varying features such as virtual channels, input/output buffering, and adaptive routing algorithms.
1. **Network Interfaces (NIs)**: A set of NoC network interfaces for connecting IPs to the NoC.
1. **Topologies:** A collection of NoC topologies, such as mesh, to enable the creation of various on-chip interconnects.
1. **Common IPs** A set of IPs used by the NoC IPs, such as FIFOs, Cuts and arbiters.
1. **Verification IPs (VIPs):** A set of VIPs to verify the correct functionality of the NoC IPs.
1. **Testbenches:** A set of testbenches to evaluate the performance of the NoC IPs, including throughput, latency.
2. **Common IPs** A set of IPs used by the NoC IPs, such as FIFOs, Cuts and arbiters.
3. **Verification IPs (VIPs):** A set of VIPs to verify the correct functionality of the NoC IPs.
4. **Testbenches:** A set of testbenches to evaluate the performance of the NoC IPs, including throughput, latency.

### Routers
| Name | Description | Doc |
Expand All @@ -113,12 +112,6 @@ This repository includes the following NoC IPs:
| [floo_axi_chimney](hw/floo_axi_chimney.sv) | A bidirectional network interface for connecting AXI4 Buses to the NoC | |
| [floo_narrow_wide_chimney](hw/floo_narrow_wide_chimney.sv) | A bidirectional network interface for connecting narrow & wide AXI Buses to the multi-link NoC | |

### Topologies
| Name | Description | Doc |
| --- | --- | --- |
| [floo_mesh](hw/floo_mesh.sv) | A mesh topology with configurable number of rows and columns | |
| [floo_mesh_ruche](hw/floo_mesh_ruche.sv) | A mesh topology with ruche channels and a configurable number of rows and columns | |

### Common IPs
| Name | Description | Doc |
| --- | --- | --- |
Expand Down
35 changes: 0 additions & 35 deletions floogen/examples/axi_pkg.yml

This file was deleted.

49 changes: 0 additions & 49 deletions floogen/examples/narrow_wide_pkg.yml

This file was deleted.

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