wip: Chimney for TCDM ports
GitHub Actions / verible-verilog-lint
failed
Jun 24, 2024 in 1s
reviewdog [verible-verilog-lint] report
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Findings (1)
hw/floo_tcdm_chimney.sv|143 col 101| Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]
Filtered Findings (0)
Annotations
Check warning on line 143 in hw/floo_tcdm_chimney.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_tcdm_chimney.sv#L143
Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]" location:{path:"./hw/floo_tcdm_chimney.sv" range:{start:{line:143 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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