wip: Floo macros
reviewdog [verible-verilog-lint] report
reported by reviewdog 🐶
Findings (22)
hw/floo_axi_chimney.sv|72 col 101| Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
hw/tb/tb_floo_rob.sv|232 col 101| Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
hw/floo_narrow_wide_router.sv|11 col 8| Declared module does not match the first dot-delimited component of file name: "floo_narrow_wide_router" [Style: file-names] [module-filename]
hw/floo_narrow_wide_router.sv|58 col 101| Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]
hw/floo_narrow_wide_router.sv|59 col 101| Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]
hw/tb/tb_floo_vc_dma_mesh.sv|29 col 101| Line length exceeds max: 100; is: 131 [Style: line-length] [line-length]
hw/tb/tb_floo_vc_dma_mesh.sv|262 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/floo_narrow_wide_chimney.sv|90 col 101| Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]
hw/floo_narrow_wide_chimney.sv|91 col 101| Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]
hw/floo_rob.sv|280 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/floo_rob.sv|325 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/floo_pkg.sv|157 col 5| Explicitly define a default case for every case statement or add unique qualifier to the case statement. [Style: case-statements] [case-missing-default]
hw/floo_pkg.sv|167 col 5| Explicitly define a default case for every case statement or add unique qualifier to the case statement. [Style: case-statements] [case-missing-default]
hw/floo_pkg.sv|193 col 101| Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]
hw/floo_pkg.sv|210 col 101| Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]
hw/tb/tb_floo_dma_mesh.sv|28 col 101| Line length exceeds max: 100; is: 131 [Style: line-length] [line-length]
hw/tb/tb_floo_dma_mesh.sv|256 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/floo_vc_narrow_wide_router.sv|83 col 101| Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]
hw/floo_vc_narrow_wide_router.sv|84 col 101| Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]
hw/floo_vc_narrow_wide_chimney.sv|106 col 101| Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]
hw/floo_vc_narrow_wide_chimney.sv|107 col 101| Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]
hw/tb/tb_floo_narrow_wide_chimney.sv|55 col 101| Line length exceeds max: 100; is: 131 [Style: line-length] [line-length]
Filtered Findings (0)
Annotations
Check warning on line 72 in hw/floo_axi_chimney.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_axi_chimney.sv#L72
Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]" location:{path:"./hw/floo_axi_chimney.sv" range:{start:{line:72 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 232 in hw/tb/tb_floo_rob.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/tb/tb_floo_rob.sv#L232
Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]" location:{path:"./hw/tb/tb_floo_rob.sv" range:{start:{line:232 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 11 in hw/floo_narrow_wide_router.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_narrow_wide_router.sv#L11
Declared module does not match the first dot-delimited component of file name: "floo_narrow_wide_router" [Style: file-names] [module-filename]
Raw output
message:"Declared module does not match the first dot-delimited component of file name: \"floo_narrow_wide_router\" [Style: file-names] [module-filename]" location:{path:"./hw/floo_narrow_wide_router.sv" range:{start:{line:11 column:8}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:11 column:8} end:{line:12}} text:"module floo_narrow_wide_router #(\n"}
Check warning on line 58 in hw/floo_narrow_wide_router.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_narrow_wide_router.sv#L58
Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]" location:{path:"./hw/floo_narrow_wide_router.sv" range:{start:{line:58 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 59 in hw/floo_narrow_wide_router.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_narrow_wide_router.sv#L59
Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]" location:{path:"./hw/floo_narrow_wide_router.sv" range:{start:{line:59 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 29 in hw/tb/tb_floo_vc_dma_mesh.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/tb/tb_floo_vc_dma_mesh.sv#L29
Line length exceeds max: 100; is: 131 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 131 [Style: line-length] [line-length]" location:{path:"./hw/tb/tb_floo_vc_dma_mesh.sv" range:{start:{line:29 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 262 in hw/tb/tb_floo_vc_dma_mesh.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/tb/tb_floo_vc_dma_mesh.sv#L262
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"./hw/tb/tb_floo_vc_dma_mesh.sv" range:{start:{line:262 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 90 in hw/floo_narrow_wide_chimney.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_narrow_wide_chimney.sv#L90
Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]" location:{path:"./hw/floo_narrow_wide_chimney.sv" range:{start:{line:90 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 91 in hw/floo_narrow_wide_chimney.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_narrow_wide_chimney.sv#L91
Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]" location:{path:"./hw/floo_narrow_wide_chimney.sv" range:{start:{line:91 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 280 in hw/floo_rob.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_rob.sv#L280
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"./hw/floo_rob.sv" range:{start:{line:280 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 325 in hw/floo_rob.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_rob.sv#L325
Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"./hw/floo_rob.sv" range:{start:{line:325 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 157 in hw/floo_pkg.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_pkg.sv#L157
Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default]
Raw output
message:"Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default]" location:{path:"./hw/floo_pkg.sv" range:{start:{line:157 column:5}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 167 in hw/floo_pkg.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_pkg.sv#L167
Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default]
Raw output
message:"Explicitly define a default case for every case statement or add `unique` qualifier to the case statement. [Style: case-statements] [case-missing-default]" location:{path:"./hw/floo_pkg.sv" range:{start:{line:167 column:5}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 193 in hw/floo_pkg.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_pkg.sv#L193
Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]" location:{path:"./hw/floo_pkg.sv" range:{start:{line:193 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 210 in hw/floo_pkg.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_pkg.sv#L210
Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]" location:{path:"./hw/floo_pkg.sv" range:{start:{line:210 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 28 in hw/tb/tb_floo_dma_mesh.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/tb/tb_floo_dma_mesh.sv#L28
Line length exceeds max: 100; is: 131 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 131 [Style: line-length] [line-length]" location:{path:"./hw/tb/tb_floo_dma_mesh.sv" range:{start:{line:28 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 256 in hw/tb/tb_floo_dma_mesh.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/tb/tb_floo_dma_mesh.sv#L256
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"./hw/tb/tb_floo_dma_mesh.sv" range:{start:{line:256 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 83 in hw/floo_vc_narrow_wide_router.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_vc_narrow_wide_router.sv#L83
Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]" location:{path:"./hw/floo_vc_narrow_wide_router.sv" range:{start:{line:83 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 84 in hw/floo_vc_narrow_wide_router.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_vc_narrow_wide_router.sv#L84
Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]" location:{path:"./hw/floo_vc_narrow_wide_router.sv" range:{start:{line:84 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 106 in hw/floo_vc_narrow_wide_chimney.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_vc_narrow_wide_chimney.sv#L106
Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 158 [Style: line-length] [line-length]" location:{path:"./hw/floo_vc_narrow_wide_chimney.sv" range:{start:{line:106 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 107 in hw/floo_vc_narrow_wide_chimney.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/floo_vc_narrow_wide_chimney.sv#L107
Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 144 [Style: line-length] [line-length]" location:{path:"./hw/floo_vc_narrow_wide_chimney.sv" range:{start:{line:107 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 55 in hw/tb/tb_floo_narrow_wide_chimney.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/tb/tb_floo_narrow_wide_chimney.sv#L55
Line length exceeds max: 100; is: 131 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 131 [Style: line-length] [line-length]" location:{path:"./hw/tb/tb_floo_narrow_wide_chimney.sv" range:{start:{line:55 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}