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VCS and Verilator support #358

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VCS and Verilator support #358

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4 changes: 2 additions & 2 deletions src/axi_sim_mem.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -116,8 +116,8 @@ module axi_sim_mem #(

monitor_t [NumPorts-1:0] mon_w, mon_r;
logic [7:0] mem[addr_t];
axi_pkg::resp_t rerr[addr_t] = '{default: axi_pkg::RESP_OKAY};
axi_pkg::resp_t werr[addr_t] = '{default: axi_pkg::RESP_OKAY};
axi_pkg::resp_t rerr[addr_t] = '{default: 2'b0};
axi_pkg::resp_t werr[addr_t] = '{default: 2'b0};

// error happened in write burst
axi_pkg::resp_t [NumPorts-1:0] error_happened = axi_pkg::RESP_OKAY;
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28 changes: 14 additions & 14 deletions src/axi_test.sv
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Expand Up @@ -226,9 +226,9 @@ package axi_test;

/// The data transferred on a beat on the AW/AR channels.
class axi_ax_beat #(
parameter AW = 32,
parameter IW = 8 ,
parameter UW = 1
parameter int AW = 32,
parameter int IW = 8 ,
parameter int UW = 1
);
rand logic [IW-1:0] ax_id = '0;
rand logic [AW-1:0] ax_addr = '0;
Expand All @@ -246,8 +246,8 @@ package axi_test;

/// The data transferred on a beat on the W channel.
class axi_w_beat #(
parameter DW = 32,
parameter UW = 1
parameter int DW = 32,
parameter int UW = 1
);
rand logic [DW-1:0] w_data = '0;
rand logic [DW/8-1:0] w_strb = '0;
Expand All @@ -257,8 +257,8 @@ package axi_test;

/// The data transferred on a beat on the B channel.
class axi_b_beat #(
parameter IW = 8,
parameter UW = 1
parameter int IW = 8,
parameter int UW = 1
);
rand logic [IW-1:0] b_id = '0;
axi_pkg::resp_t b_resp = '0;
Expand All @@ -267,9 +267,9 @@ package axi_test;

/// The data transferred on a beat on the R channel.
class axi_r_beat #(
parameter DW = 32,
parameter IW = 8 ,
parameter UW = 1
parameter int DW = 32,
parameter int IW = 8 ,
parameter int UW = 1
);
rand logic [IW-1:0] r_id = '0;
rand logic [DW-1:0] r_data = '0;
Expand Down Expand Up @@ -747,7 +747,7 @@ package axi_test;
len_t max_len;
burst_t allowed_bursts[$];

semaphore cnt_sem;
std::semaphore cnt_sem;

ax_beat_t aw_queue[$],
w_queue[$],
Expand Down Expand Up @@ -1037,7 +1037,7 @@ package axi_test;
automatic addr_t addr_mask;
// In an exclusive burst, the number of bytes to be transferred must be a power of 2, i.e.,
// 1, 2, 4, 8, 16, 32, 64, or 128 bytes, and the burst length must not exceed 16 transfers.
static int unsigned ul = (AXI_STRB_WIDTH < 8) ? 4 + $clog2(AXI_STRB_WIDTH) : 7;
int unsigned ul = (AXI_STRB_WIDTH < 8) ? 4 + $clog2(AXI_STRB_WIDTH) : 7;
rand_success = std::randomize(n_bytes) with {
n_bytes >= 1;
n_bytes <= ul;
Expand Down Expand Up @@ -1848,8 +1848,8 @@ package axi_test;
typedef axi_driver_t::r_beat_t r_beat_t;

axi_driver_t drv;
mailbox aw_mbx = new, w_mbx = new, b_mbx = new,
ar_mbx = new, r_mbx = new;
std::mailbox aw_mbx = new, w_mbx = new, b_mbx = new,
ar_mbx = new, r_mbx = new;

function new(
virtual AXI_BUS_DV #(
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2 changes: 1 addition & 1 deletion test/tb_axi_dw_pkg.sv
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Expand Up @@ -134,7 +134,7 @@ package tb_axi_dw_pkg ;
longint unsigned tests_expected;
longint unsigned tests_conducted;
longint unsigned tests_failed;
semaphore cnt_sem;
std::semaphore cnt_sem;

// Queues and FIFOs to hold the expected AXIDs

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2 changes: 1 addition & 1 deletion test/tb_axi_xbar_pkg.sv
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Expand Up @@ -101,7 +101,7 @@ package tb_axi_xbar_pkg;
longint unsigned tests_expected;
longint unsigned tests_conducted;
longint unsigned tests_failed;
semaphore cnt_sem;
std::semaphore cnt_sem;

//-----------------------------------------
// Constructor
Expand Down