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rstn fix
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chaoqun-liang committed Sep 11, 2024
1 parent f406922 commit 1d27083
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Showing 3 changed files with 12 additions and 11 deletions.
5 changes: 3 additions & 2 deletions hw/cheshire_soc.sv
Original file line number Diff line number Diff line change
Expand Up @@ -1301,6 +1301,7 @@ module cheshire_soc import cheshire_pkg::*; #(
// ETHERNET //
////////////////
if (Cfg.Ethernet) begin : gen_ethernet
logic eth_int_n, eth_pme_n;
eth_idma_wrap#(
.DataWidth ( Cfg.AxiDataWidth ),

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[verible-verilog-lint] hw/cheshire_soc.sv#L1306

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:1306  column:50}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:1306  column:50}  end:{line:1307}}  text:"      .DataWidth           ( Cfg.AxiDataWidth  ),\n"}
.AddrWidth ( Cfg.AddrWidth ),
Expand Down Expand Up @@ -1329,8 +1330,8 @@ module cheshire_soc import cheshire_pkg::*; #(
.phy_txd_o ( eth_txd_o ),
.phy_tx_ctl_o ( eth_txctl_o ),
.phy_resetn_o ( eth_rstn_o ),

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[verible-verilog-lint] hw/cheshire_soc.sv#L1332

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:1332  column:45}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:1332  column:45}  end:{line:1333}}  text:"      .phy_resetn_o        ( eth_rstn_o   ),\n"}
.phy_intn_i ( 1'b1 ),
.phy_pme_i ( 1'b1 ),
.phy_intn_i ( eth_int_n ),
.phy_pme_i ( eth_pme_n ),
.phy_mdio_i ( eth_mdio_i ),
.phy_mdio_o ( eth_mdio_o ),
.phy_mdio_oe ( eth_mdio_oe ),
Expand Down
16 changes: 8 additions & 8 deletions sw/boot/cheshire.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -107,13 +107,13 @@
riscv,ndev = <51>;
reg = <0x0 0x4000000 0x0 0x4000000>;
};
#eth: idma-eth@300c000 {
#compatible = "idma-eth";
#device_type = "network";
#interrupt-parent = <&PLIC0>;
#interrupts = <19>;
#local-mac-address = [00 18 3e 02 e3 7f]; // This needs to change if more than one GenesysII on a VLAN
#reg = <0x0 0x300c000 0x0 0x1000>;
#};
eth: lowrisc-eth@300c000 {
compatible = "lowrisc-eth";
device_type = "network";
interrupt-parent = <&PLIC0>;
interrupts = <19>;
local-mac-address = [00 18 3e 02 e3 7f]; // This needs to change if more than one GenesysII on a VLAN
reg = <0x0 0x300c000 0x0 0x1000>;
};
};
};
2 changes: 1 addition & 1 deletion target/xilinx/src/cheshire_top_xilinx.sv
Original file line number Diff line number Diff line change
Expand Up @@ -496,7 +496,7 @@ module cheshire_top_xilinx (
.eth_txck_o ( eth_txck ),
.eth_txd_o ( eth_txd ),
.eth_txctl_o ( eth_txctl ),
.eth_rstn_o ( eth_rstn ),
.eth_rstn_o ( eth_rst_n ),
.eth_mdio_i ( eth_mdio_i ),
.eth_mdio_o ( eth_mdio_o ),
.eth_mdio_oe ( eth_mdio_oe ),
Expand Down

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