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Add VCU118 Support #153

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Add VCU118 Support #153

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77c2f87
Add support for VCU118
Oct 3, 2024
44315f2
Adjust vcu118.xdc and revert vcu128.xdc
Oct 11, 2024
9acf498
Fix AddrWidth for VCU118 target
Oct 11, 2024
b3f156c
Mutualize DDR4 instantiation
Oct 11, 2024
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20 changes: 20 additions & 0 deletions sw/boot/cheshire.vcu118.dts
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// Copyright 2024 ETH Zurich and University of Bologna.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51
//
// Cyril Koenig <[email protected]>
// Mojtaba Rostami <[email protected]>

/include/ "cheshire.dtsi"

&spi {
boot-with = <0>;
mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>; // CS
spi-max-frequency = <25000000>;
voltage-ranges = <3300 3300>;
clock-frequency = <1000000>;
disable-wp;
};
};
213 changes: 213 additions & 0 deletions target/xilinx/constraints/vcu118.xdc
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# Copyright 2022 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
#
# Nicole Narr <[email protected]>
# Christopher Reinwardt <[email protected]>
# Cyril Koenig <[email protected]>
# Paul Scheffler <[email protected]>

#############
# Sys Clock #
#############

# 125 MHz input clock
set SYS_TCK 8
create_clock -period $SYS_TCK -name sys_clk [get_ports sys_clk_p]

# SoC clock is generated by clock wizard and its constraints
set SOC_TCK 20.0
set soc_clk [get_clocks -of_objects [get_pins i_clkwiz/clk_50]]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets soc_clk]


#######
# MIG #
#######

# Dram axi clock : 200 MHz (defined by MIG constraints)
set MIG_TCK 5

# False-path incoming reset
set MIG_RST_I [get_pin i_dram_wrapper/i_dram/c0_ddr4_aresetn]
set_false_path -hold -setup -through $MIG_RST_I

# Constrain outgoing reset
set MIG_RST_O [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst]
set_false_path -hold -through $MIG_RST_O
set_max_delay -through $MIG_RST_O $MIG_TCK

# Limit delay across DRAM CDC (hold already false-pathed)
# tclint-disable line-length
set_max_delay -datapath_only \
-from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \
-to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] $MIG_TCK
set_max_delay -datapath_only \
-from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \
-to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $MIG_TCK
# tclint-enable line-length

###############
# Assign Pins #
###############

# Clock diff @ 125MHz
set_property IOSTANDARD LVDS [get_ports sys_clk_n]
set_property IOSTANDARD LVDS [get_ports sys_clk_p]
set_property PACKAGE_PIN AY24 [get_ports sys_clk_p]
set_property PACKAGE_PIN AY23 [get_ports sys_clk_n]

# tclint-disable line-length, spacing

set_property PACKAGE_PIN AW25 [get_ports uart_rx_i]
set_property IOSTANDARD LVCMOS18 [get_ports uart_rx_i]
set_property PACKAGE_PIN BB21 [get_ports uart_tx_o]
set_property IOSTANDARD LVCMOS18 [get_ports uart_tx_o]


# Active high reset (GPIO_SW_N)
set_property PACKAGE_PIN BB24 [get_ports sys_reset]
set_property IOSTANDARD LVCMOS18 [get_ports sys_reset]

# tclint-enable line-length, spacing

# SD Card
set_property -dict {PACKAGE_PIN AT15 IOSTANDARD LVCMOS12} [get_ports sd_cd_i]
set_property -dict {PACKAGE_PIN AY15 IOSTANDARD LVCMOS12} [get_ports sd_cmd_o]
set_property -dict {PACKAGE_PIN AW15 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[0]}]
set_property -dict {PACKAGE_PIN AV16 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[1]}]
set_property -dict {PACKAGE_PIN AU16 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[2]}]
set_property -dict {PACKAGE_PIN AY14 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[3]}]
set_property -dict {PACKAGE_PIN AV15 IOSTANDARD LVCMOS12} [get_ports sd_sclk_o]


## DDR4

set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_n]
set_property PACKAGE_PIN E12 [get_ports c0_sys_clk_p]
set_property PACKAGE_PIN D12 [get_ports c0_sys_clk_n]
set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_p]

set_property PACKAGE_PIN E13 [get_ports c0_ddr4_act_n]
set_property PACKAGE_PIN D14 [get_ports {c0_ddr4_adr[0]}]
set_property PACKAGE_PIN C12 [get_ports {c0_ddr4_adr[10]}]
set_property PACKAGE_PIN B13 [get_ports {c0_ddr4_adr[11]}]
set_property PACKAGE_PIN C13 [get_ports {c0_ddr4_adr[12]}]
set_property PACKAGE_PIN D15 [get_ports {c0_ddr4_adr[13]}]
set_property PACKAGE_PIN H14 [get_ports {c0_ddr4_adr[14]}]
set_property PACKAGE_PIN H15 [get_ports {c0_ddr4_adr[15]}]
set_property PACKAGE_PIN F15 [get_ports {c0_ddr4_adr[16]}]
set_property PACKAGE_PIN B15 [get_ports {c0_ddr4_adr[1]}]
set_property PACKAGE_PIN B16 [get_ports {c0_ddr4_adr[2]}]
set_property PACKAGE_PIN C14 [get_ports {c0_ddr4_adr[3]}]
set_property PACKAGE_PIN C15 [get_ports {c0_ddr4_adr[4]}]
set_property PACKAGE_PIN A13 [get_ports {c0_ddr4_adr[5]}]
set_property PACKAGE_PIN A14 [get_ports {c0_ddr4_adr[6]}]
set_property PACKAGE_PIN A15 [get_ports {c0_ddr4_adr[7]}]
set_property PACKAGE_PIN A16 [get_ports {c0_ddr4_adr[8]}]
set_property PACKAGE_PIN B12 [get_ports {c0_ddr4_adr[9]}]
set_property PACKAGE_PIN G15 [get_ports {c0_ddr4_ba[0]}]
set_property PACKAGE_PIN G13 [get_ports {c0_ddr4_ba[1]}]
set_property PACKAGE_PIN H13 [get_ports {c0_ddr4_bg[0]}]
set_property PACKAGE_PIN F14 [get_ports {c0_ddr4_ck_t[0]}]
set_property PACKAGE_PIN E14 [get_ports {c0_ddr4_ck_c[0]}]
set_property PACKAGE_PIN A10 [get_ports {c0_ddr4_cke[0]}]
set_property PACKAGE_PIN F13 [get_ports {c0_ddr4_cs_n[0]}]
set_property PACKAGE_PIN G11 [get_ports {c0_ddr4_dm_dbi_n[0]}]
set_property PACKAGE_PIN R18 [get_ports {c0_ddr4_dm_dbi_n[1]}]
set_property PACKAGE_PIN K17 [get_ports {c0_ddr4_dm_dbi_n[2]}]
set_property PACKAGE_PIN G18 [get_ports {c0_ddr4_dm_dbi_n[3]}]
set_property PACKAGE_PIN B18 [get_ports {c0_ddr4_dm_dbi_n[4]}]
set_property PACKAGE_PIN P20 [get_ports {c0_ddr4_dm_dbi_n[5]}]
set_property PACKAGE_PIN L23 [get_ports {c0_ddr4_dm_dbi_n[6]}]
set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}]

set_property PACKAGE_PIN F11 [get_ports {c0_ddr4_dq[0]}]
set_property PACKAGE_PIN M18 [get_ports {c0_ddr4_dq[10]}]
set_property PACKAGE_PIN M17 [get_ports {c0_ddr4_dq[11]}]
set_property PACKAGE_PIN N19 [get_ports {c0_ddr4_dq[12]}]
set_property PACKAGE_PIN N18 [get_ports {c0_ddr4_dq[13]}]
set_property PACKAGE_PIN N17 [get_ports {c0_ddr4_dq[14]}]
set_property PACKAGE_PIN M16 [get_ports {c0_ddr4_dq[15]}]
set_property PACKAGE_PIN L16 [get_ports {c0_ddr4_dq[16]}]
set_property PACKAGE_PIN K16 [get_ports {c0_ddr4_dq[17]}]
set_property PACKAGE_PIN L18 [get_ports {c0_ddr4_dq[18]}]
set_property PACKAGE_PIN K18 [get_ports {c0_ddr4_dq[19]}]
set_property PACKAGE_PIN E11 [get_ports {c0_ddr4_dq[1]}]
set_property PACKAGE_PIN J17 [get_ports {c0_ddr4_dq[20]}]
set_property PACKAGE_PIN H17 [get_ports {c0_ddr4_dq[21]}]
set_property PACKAGE_PIN H19 [get_ports {c0_ddr4_dq[22]}]
set_property PACKAGE_PIN H18 [get_ports {c0_ddr4_dq[23]}]
set_property PACKAGE_PIN F19 [get_ports {c0_ddr4_dq[24]}]
set_property PACKAGE_PIN F18 [get_ports {c0_ddr4_dq[25]}]
set_property PACKAGE_PIN E19 [get_ports {c0_ddr4_dq[26]}]
set_property PACKAGE_PIN E18 [get_ports {c0_ddr4_dq[27]}]
set_property PACKAGE_PIN G20 [get_ports {c0_ddr4_dq[28]}]
set_property PACKAGE_PIN F20 [get_ports {c0_ddr4_dq[29]}]
set_property PACKAGE_PIN F10 [get_ports {c0_ddr4_dq[2]}]
set_property PACKAGE_PIN E17 [get_ports {c0_ddr4_dq[30]}]
set_property PACKAGE_PIN D16 [get_ports {c0_ddr4_dq[31]}]
set_property PACKAGE_PIN D17 [get_ports {c0_ddr4_dq[32]}]
set_property PACKAGE_PIN C17 [get_ports {c0_ddr4_dq[33]}]
set_property PACKAGE_PIN C19 [get_ports {c0_ddr4_dq[34]}]
set_property PACKAGE_PIN C18 [get_ports {c0_ddr4_dq[35]}]
set_property PACKAGE_PIN D20 [get_ports {c0_ddr4_dq[36]}]
set_property PACKAGE_PIN D19 [get_ports {c0_ddr4_dq[37]}]
set_property PACKAGE_PIN C20 [get_ports {c0_ddr4_dq[38]}]
set_property PACKAGE_PIN B20 [get_ports {c0_ddr4_dq[39]}]
set_property PACKAGE_PIN F9 [get_ports {c0_ddr4_dq[3]}]
set_property PACKAGE_PIN N23 [get_ports {c0_ddr4_dq[40]}]
set_property PACKAGE_PIN M23 [get_ports {c0_ddr4_dq[41]}]
set_property PACKAGE_PIN R21 [get_ports {c0_ddr4_dq[42]}]
set_property PACKAGE_PIN P21 [get_ports {c0_ddr4_dq[43]}]
set_property PACKAGE_PIN R22 [get_ports {c0_ddr4_dq[44]}]
set_property PACKAGE_PIN P22 [get_ports {c0_ddr4_dq[45]}]
set_property PACKAGE_PIN T23 [get_ports {c0_ddr4_dq[46]}]
set_property PACKAGE_PIN R23 [get_ports {c0_ddr4_dq[47]}]
set_property PACKAGE_PIN K24 [get_ports {c0_ddr4_dq[48]}]
set_property PACKAGE_PIN J24 [get_ports {c0_ddr4_dq[49]}]
set_property PACKAGE_PIN H12 [get_ports {c0_ddr4_dq[4]}]
set_property PACKAGE_PIN M21 [get_ports {c0_ddr4_dq[50]}]
set_property PACKAGE_PIN L21 [get_ports {c0_ddr4_dq[51]}]
set_property PACKAGE_PIN K21 [get_ports {c0_ddr4_dq[52]}]
set_property PACKAGE_PIN J21 [get_ports {c0_ddr4_dq[53]}]
set_property PACKAGE_PIN K22 [get_ports {c0_ddr4_dq[54]}]
set_property PACKAGE_PIN J22 [get_ports {c0_ddr4_dq[55]}]
set_property PACKAGE_PIN H23 [get_ports {c0_ddr4_dq[56]}]
set_property PACKAGE_PIN H22 [get_ports {c0_ddr4_dq[57]}]
set_property PACKAGE_PIN E23 [get_ports {c0_ddr4_dq[58]}]
set_property PACKAGE_PIN E22 [get_ports {c0_ddr4_dq[59]}]
set_property PACKAGE_PIN G12 [get_ports {c0_ddr4_dq[5]}]
set_property PACKAGE_PIN F21 [get_ports {c0_ddr4_dq[60]}]
set_property PACKAGE_PIN E21 [get_ports {c0_ddr4_dq[61]}]
set_property PACKAGE_PIN F24 [get_ports {c0_ddr4_dq[62]}]
set_property PACKAGE_PIN F23 [get_ports {c0_ddr4_dq[63]}]

set_property PACKAGE_PIN E9 [get_ports {c0_ddr4_dq[6]}]
set_property PACKAGE_PIN D9 [get_ports {c0_ddr4_dq[7]}]
set_property PACKAGE_PIN R19 [get_ports {c0_ddr4_dq[8]}]
set_property PACKAGE_PIN P19 [get_ports {c0_ddr4_dq[9]}]

set_property PACKAGE_PIN D11 [get_ports {c0_ddr4_dqs_t[0]}]
set_property PACKAGE_PIN D10 [get_ports {c0_ddr4_dqs_c[0]}]
set_property PACKAGE_PIN P17 [get_ports {c0_ddr4_dqs_t[1]}]
set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_dqs_c[1]}]
set_property PACKAGE_PIN K19 [get_ports {c0_ddr4_dqs_t[2]}]
set_property PACKAGE_PIN J19 [get_ports {c0_ddr4_dqs_c[2]}]
set_property PACKAGE_PIN F16 [get_ports {c0_ddr4_dqs_t[3]}]
set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_dqs_c[3]}]
set_property PACKAGE_PIN A19 [get_ports {c0_ddr4_dqs_t[4]}]
set_property PACKAGE_PIN A18 [get_ports {c0_ddr4_dqs_c[4]}]
set_property PACKAGE_PIN N22 [get_ports {c0_ddr4_dqs_t[5]}]
set_property PACKAGE_PIN M22 [get_ports {c0_ddr4_dqs_c[5]}]
set_property PACKAGE_PIN M20 [get_ports {c0_ddr4_dqs_t[6]}]
set_property PACKAGE_PIN L20 [get_ports {c0_ddr4_dqs_c[6]}]
set_property PACKAGE_PIN H24 [get_ports {c0_ddr4_dqs_t[7]}]
set_property PACKAGE_PIN G23 [get_ports {c0_ddr4_dqs_c[7]}]

set_property PACKAGE_PIN C8 [get_ports {c0_ddr4_odt[0]}]
set_property PACKAGE_PIN N20 [get_ports c0_ddr4_reset_n]

##########


5 changes: 5 additions & 0 deletions target/xilinx/scripts/common.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,11 @@ set fpart(vcu128) "xcvu37p-fsvh2892-2L-e"
set hwdev(vcu128) "xcvu37p_0"
set cfgmp(vcu128) "mt25qu02g-spi-x1_x2_x4"

# vcu118 board params
set bpart(vcu118) "xilinx.com:vcu118:part0:2.4"
set fpart(vcu118) "xcvu9p-flga2104-2L-e"
set hwdev(vcu118) "xcvu9p_0"


# Initialize an implementation project
proc init_impl {xilinx_root argc argv} {
Expand Down
75 changes: 75 additions & 0 deletions target/xilinx/scripts/impl_ip.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -87,6 +87,43 @@ switch $proj {
CONFIG.CLKOUT4_PHASE_ERROR {89.971} \
] [get_ips $proj]
}
vcu118 {
set_property -dict [list \
CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \
CONFIG.RESET_BOARD_INTERFACE {Custom} \
CONFIG.USE_RESET {true} \
CONFIG.PRIM_SOURCE {No_buffer} \
CONFIG.PRIM_IN_FREQ {125.000} \
CONFIG.CLKOUT1_USED {true} \
CONFIG.CLKOUT2_USED {true} \
CONFIG.CLKOUT3_USED {true} \
CONFIG.CLKOUT4_USED {true} \
CONFIG.CLK_OUT1_PORT {clk_50} \
CONFIG.CLK_OUT2_PORT {clk_48} \
CONFIG.CLK_OUT3_PORT {clk_20} \
CONFIG.CLK_OUT4_PORT {clk_10} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50.000} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {48.000} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \
CONFIG.MMCM_CLKFBOUT_MULT_F {48.000} \
CONFIG.MMCM_CLKIN1_PERIOD {8.000} \
CONFIG.MMCM_CLKOUT0_DIVIDE_F {24.000} \
CONFIG.MMCM_CLKOUT1_DIVIDE {25} \
CONFIG.MMCM_CLKOUT2_DIVIDE {60} \
CONFIG.MMCM_CLKOUT3_DIVIDE {120} \
CONFIG.MMCM_CLKOUT4_DIVIDE {1} \
CONFIG.NUM_OUT_CLKS {4} \
CONFIG.CLKOUT1_JITTER {196.543} \
CONFIG.CLKOUT1_PHASE_ERROR {222.305} \
CONFIG.CLKOUT2_JITTER {197.699} \
CONFIG.CLKOUT2_PHASE_ERROR {222.305} \
CONFIG.CLKOUT3_JITTER {227.146} \
CONFIG.CLKOUT3_PHASE_ERROR {222.305} \
CONFIG.CLKOUT4_JITTER {261.444} \
CONFIG.CLKOUT4_PHASE_ERROR {222.305} \
] [get_ips $proj]
}
default { nocfgexit $proj $board }
}
}
Expand Down Expand Up @@ -116,6 +153,17 @@ switch $proj {
CONFIG.C_NUM_PROBE_IN {0} \
] [get_ips $proj]
}
vcu118 {
set_property -dict [list \
CONFIG.C_NUM_PROBE_OUT {3} \
CONFIG.C_PROBE_OUT0_INIT_VAL {0x0} \
CONFIG.C_PROBE_OUT1_INIT_VAL {0x1} \
CONFIG.C_PROBE_OUT2_INIT_VAL {0x1} \
CONFIG.C_PROBE_OUT1_WIDTH {2} \
CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \
CONFIG.C_NUM_PROBE_IN {0} \
] [get_ips $proj]
}
default { nocfgexit $proj $board }
}
}
Expand Down Expand Up @@ -162,6 +210,33 @@ switch $proj {
CONFIG.C0.DDR4_AxiSelection {true} \
] [get_ips $proj]
}
vcu118 {
set_property -dict [list \
CONFIG.C0.DDR4_Clamshell {false} \
CONFIG.C0_DDR4_BOARD_INTERFACE {Custom} \
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Why not choosing one of the ddr4 interfaces proposed by Vivado? This makes the constraint file less verbose.

CONFIG.System_Clock {Differential} \
CONFIG.Reference_Clock {No_Buffer} \
CONFIG.C0.DDR4_InputClockPeriod {4000} \
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \
CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-075E} \
CONFIG.C0.DDR4_DataWidth {64} \
CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \
CONFIG.C0.DDR4_Ecc {false} \
CONFIG.C0.DDR4_AxiDataWidth {512} \
CONFIG.C0.DDR4_AxiAddressWidth {31} \
CONFIG.C0.DDR4_AxiIDWidth {8} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \
CONFIG.C0.BANK_GROUP_WIDTH {1} \
CONFIG.C0.CS_WIDTH {1} \
CONFIG.C0.DDR4_AxiSelection {true} \
CONFIG.C0.DDR4_CasWriteLatency {9} \
CONFIG.C0.DDR4_TimePeriod {1250} \
CONFIG.C0.DDR4_Specify_MandD {true} \
CONFIG.C0.DDR4_CLKFBOUT_MULT {8} \
CONFIG.C0.DDR4_DIVCLK_DIVIDE {2} \
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \
] [get_ips $proj]
}
default { nocfgexit $proj $board }
}
}
Expand Down
5 changes: 5 additions & 0 deletions target/xilinx/src/cheshire_top_xilinx.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@
// Cyril Koenig <[email protected]>
// Yann Picod <[email protected]>
// Paul Scheffler <[email protected]>
// Mojtaba Rostami <[email protected]>

`include "cheshire/typedef.svh"
`include "phy_definitions.svh"
Expand Down Expand Up @@ -52,7 +53,9 @@ module cheshire_top_xilinx import cheshire_pkg::*; (
input logic sd_cd_i,
output logic sd_cmd_o,
inout wire [3:0] sd_d_io,
`ifndef TARGET_VCU118
output logic sd_reset_o,
`endif
output logic sd_sclk_o,
`endif

Expand Down Expand Up @@ -257,8 +260,10 @@ module cheshire_top_xilinx import cheshire_pkg::*; (
logic [3:0] spi_sd_en;

`ifdef USE_SD
`ifndef TARGET_VCU118
// Assert reset low => Apply power to the SD Card
assign sd_reset_o = 1'b0;
`endif
// SCK - SD CLK signal
assign sd_sclk_o = spi_sck_en ? spi_sck_soc : 1'b1;
// CS - SD DAT3 signal
Expand Down
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