Verilator

.clang-format

@@ -0,0 +1,7 @@
+IndentWidth: 4
+ColumnLimit: 100
+AlignEscapedNewlines: DontAlign
+SortIncludes: false
+AllowShortFunctionsOnASingleLine: None
+AllowShortIfStatementsOnASingleLine: true
+AllowShortLoopsOnASingleLine: true

Bender.yml

@@ -49,3 +49,7 @@ sources:
     files:
       - target/xilinx/src/fan_ctrl.sv
       - target/xilinx/src/cheshire_top_xilinx.sv
+
+  - target: verilator
+    files:
+      - target/verilator/src/cheshire_testharness.sv

Makefile

@@ -6,7 +6,7 @@
 # Christopher Reinwardt <[email protected]>
 # Paul Scheffler <[email protected]>
 
-CHS_ROOT ?= .
+CHS_ROOT ?= $(shell pwd)
 
 include cheshire.mk
 

cheshire.mk

@@ -151,3 +151,15 @@ $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl: Bender.yml
 	$(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 > $@
 
 chs-xilinx-all: $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl
+
+
+#############
+# Verilator #
+#############
+
+.PHONY: chs-source-env
+
+chs-install-verilator:
+	$(CHS_ROOT)/target/verilator/scripts/install-verilator.sh
+
+include $(CHS_ROOT)/target/verilator/verilator.mk

hw/cheshire_pkg.sv

@@ -431,7 +431,7 @@ package cheshire_pkg;
     LlcAmoPostCut     : 1,
     LlcOutConnect     : 1,
     LlcOutRegionStart : 'h8000_0000,
-    LlcOutRegionEnd   : 'h1_0000_0000,
+    LlcOutRegionEnd   : 64'h1_0000_0000,
     // VGA: RGB332
     VgaRedWidth       : 3,
     VgaGreenWidth     : 3,
@@ -442,8 +442,8 @@ package cheshire_pkg;
     SlinkMaxTxnsPerId : 4,
     SlinkMaxUniqIds   : 4,
     SlinkMaxClkDiv    : 1024,
-    SlinkRegionStart  : 'h1_0000_0000,
-    SlinkRegionEnd    : 'h2_0000_0000,
+    SlinkRegionStart  : 64'h1_0000_0000,
+    SlinkRegionEnd    : 64'h2_0000_0000,
     SlinkTxAddrMask   : 'hFFFF_FFFF,
     SlinkTxAddrDomain : 'h0000_0000,
     SlinkUserAmoBit   : 1,  // Upper atomics bit for serial link

target/verilator/.gitignore

@@ -0,0 +1,3 @@
+install/
+obj_dir/
+build/

target/verilator/patches/permutations.patch

@@ -0,0 +1,59 @@
+--- target/verilator/build/cheshire_testharness.pickle.sv	2023-05-23 16:31:40.575735498 +0200
++++ target/verilator/build/cheshire_testharness.pickle_2.sv	2023-05-23 16:32:14.127033084 +0200
+@@ -2330,31 +2330,31 @@
+     longint unsigned rand_number = (A * seed + C) % M;
+
+     // do it for each round
+-    for (int unsigned r = 0; r < NoRounds; r++) begin
+-      // initialize the index array
+-      for (int unsigned i = 0; i < InpWidth; i++) begin
+-        indices[r][i] = i;
+-      end
+-      // do the shuffling
+-      for (int unsigned i = 0; i < InpWidth; i++) begin
+-        // get the 'random' number
+-        if (i > 0) begin
+-          rand_number = (A * rand_number + C) % M;
+-          index = rand_number % i;
+-        end
+-        // do the shuffling
+-        if (i != index) begin
+-          perm_array[r][i]     = perm_array[r][index];
+-          perm_array[r][index] = indices[r][i];
+-        end
+-      end
+-      // advance the PRG a bit
+-      rand_number = (A * rand_number + C) % M;
+-      advance     = rand_number % NoRounds;
+-      for (int unsigned i = 0; i < advance; i++) begin
+-        rand_number = (A * rand_number + C) % M;
+-      end
+-    end
++    // for (int unsigned r = 0; r < NoRounds; r++) begin
++    //   // initialize the index array
++    //   for (int unsigned i = 0; i < InpWidth; i++) begin
++    //     indices[r][i] = i;
++    //   end
++    //   // do the shuffling
++    //   for (int unsigned i = 0; i < InpWidth; i++) begin
++    //     // get the 'random' number
++    //     if (i > 0) begin
++    //       rand_number = (A * rand_number + C) % M;
++    //       index = rand_number % i;
++    //     end
++    //     // do the shuffling
++    //     if (i != index) begin
++    //       perm_array[r][i]     = perm_array[r][index];
++    //       perm_array[r][index] = indices[r][i];
++    //     end
++    //   end
++    //   // advance the PRG a bit
++    //   rand_number = (A * rand_number + C) % M;
++    //   advance     = rand_number % NoRounds;
++    //   for (int unsigned i = 0; i < advance; i++) begin
++    //     rand_number = (A * rand_number + C) % M;
++    //   end
++    // end
+     return perm_array;
+   endfunction : get_permutations
+

target/verilator/patches/reg_bus_interface_ugly_copy.sv

@@ -0,0 +1,22 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+interface REG_BUS #(
+  /// The width of the address.
+  parameter int ADDR_WIDTH = -1,
+  /// The width of the data.
+  parameter int DATA_WIDTH = -1
+)(
+  input logic clk_i
+);
+  logic [ADDR_WIDTH-1:0]   addr;
+  logic                    write; // 0=read, 1=write
+  logic [DATA_WIDTH-1:0]   rdata;
+  logic [DATA_WIDTH-1:0]   wdata;
+  logic [DATA_WIDTH/8-1:0] wstrb; // byte-wise strobe
+  logic                    error; // 0=ok, 1=error
+  logic                    valid;
+  logic                    ready;
+  modport in  (input  addr, write, wdata, wstrb, valid, output rdata, error, ready);
+  modport out (output addr, write, wdata, wstrb, valid, input  rdata, error, ready);
+endinterface

target/verilator/scripts/install-verilator.sh

@@ -0,0 +1,109 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+# inspired from https://github.com/zchamski/core-v-verif/blob/046a50d58648bafdb2263dee53e1043e83057284/cva6/regress/install-verilator.sh
+# Copyright 2021 Thales DIS design services SAS
+# Original Author: Jean-Roch COULON - Thales
+# Heavily adapted by Jannis Schönleber - ETH Zurich
+
+set -e
+
+export RISCV="/usr/pack/riscv-1.0-kgf/riscv64-gcc-11.2.0"
+export PATH="${RISCV}/bin/:$PATH"    # 64-bit
+
+export LIBRARY_PATH=$RISCV/lib
+export LD_LIBRARY_PATH=$RISCV/lib
+export C_INCLUDE_PATH=$RISCV/include
+export CPLUS_INCLUDE_PATH=$RISCV/include
+
+export TOP=${PWD}
+
+export VERILATOR_BUILD_DIR=${TOP}/target/verilator/install/verilator
+export PATH="$VERILATOR_INSTALL_DIR/bin:$PATH"
+
+
+
+# install help2man on our internal machines it is not installed
+# check if help2man is installed
+if ! command -v help2man &> /dev/null
+then
+    echo "help2man could not be found, installing it"
+    HELP2MAN_INSTALL_DIR=${TOP}/target/verilator/install/help2man
+    wget https://ftp.gnu.org/gnu/help2man/help2man-1.49.3.tar.xz -O /tmp/help2man.tar.xz
+    tar -xf /tmp/help2man.tar.xz -C /tmp
+    cd /tmp/help2man-1.49.3
+    ./configure  --prefix=${HELP2MAN_INSTALL_DIR}
+    make
+    make install
+    export PATH=${HELP2MAN_INSTALL_DIR}/bin:$PATH
+fi
+
+
+# number of parallel jobs to use for make commands and simulation
+export NUM_JOBS=16
+
+if [ -z ${NUM_JOBS} ]; then
+    NUM_JOBS=1
+fi
+
+# Ensure the location of tools is known (usually, .../core-v-verif/tools).
+if [ -z "$TOP" ]; then
+  echo "Error: location of core-v-verif 'tools' tree (\$TOP) is not defined."
+  return
+fi
+
+VERILATOR_REPO="https://github.com/verilator/verilator.git"
+VERILATOR_BRANCH="master"
+# Use the release tag instead of a full SHA1 hash.
+VERILATOR_HASH="v5.010"
+VERILATOR_PATCH="$TOP/target/verilator/patches/verilator-v5.patch"
+
+# Unset historical variable VERILATOR_ROOT as it collides with the build process.
+if [ -n "$VERILATOR_ROOT" ]; then
+  unset VERILATOR_ROOT
+fi
+
+# Define the default src+build location of Verilator.
+# No need to force this location in Continuous Integration scripts.
+if [ -z "$VERILATOR_BUILD_DIR" ]; then
+  export VERILATOR_BUILD_DIR=${TOP}/target/verilator/install/verilator
+fi
+
+# Define the default installation location of Verilator: one level up
+# from the source tree in the core-v-verif tree.
+# Continuous Integration may need to override this particular variable
+# to use a preinstalled build of Verilator.
+if [ -z "$VERILATOR_INSTALL_DIR" ]; then
+  export VERILATOR_INSTALL_DIR=$(dirname ${VERILATOR_BUILD_DIR})
+fi
+
+# Build and install Verilator only if not already installed at the expected
+# location $VERILATOR_INSTALL_DIR.
+if [ ! -f "$VERILATOR_INSTALL_DIR/bin/verilator" ]; then
+    echo "Building Verilator in $VERILATOR_BUILD_DIR..."
+    echo "Verilator will be installed in $VERILATOR_INSTALL_DIR"
+    echo "VERILATOR_REPO=$VERILATOR_REPO"
+    echo "VERILATOR_BRANCH=$VERILATOR_BRANCH"
+    echo "VERILATOR_HASH=$VERILATOR_HASH"
+    echo "VERILATOR_PATCH=$VERILATOR_PATCH"
+    mkdir -p $VERILATOR_BUILD_DIR
+    cd $VERILATOR_BUILD_DIR
+    # Clone only if the ".git" directory does not exist.
+    # Do not remove the content arbitrarily if ".git" does not exist in order
+    # to preserve user content - let git fail instead.
+    [ -d .git ] || git clone $VERILATOR_REPO -b $VERILATOR_BRANCH .
+    git checkout $VERILATOR_HASH
+    # if [ ! -z "$VERILATOR_PATCH" ] ; then
+    #   # git apply $VERILATOR_PATCH || true
+    # fi
+    # Generate the config script and configure Verilator.
+    autoconf && ./configure --prefix="$VERILATOR_INSTALL_DIR" && make -j${NUM_JOBS}
+    # FORNOW: Accept failure in 'make test' (segfault issue on Debian10)
+    # make test || true
+    echo "Installing Verilator in $VERILATOR_INSTALL_DIR..."
+    make install
+    echo "VERILATOR is installed"
+else
+    echo "Using Verilator from cached directory $VERILATOR_INSTALL_DIR."
+fi
+

target/verilator/src/cheshire.cpp

@@ -0,0 +1,96 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Modified version of the CVA6 testbench
+// (https://github.com/openhwgroup/cva6,
+// 99acdc271b90ce5abeb1b682eff4f999d0977ff4)
+//
+// Jannis Schönleber
+
+#include "Vcheshire_testharness.h"
+#include "verilated.h"
+#include <verilated_vcd_c.h>
+#if (VERILATOR_VERSION_INTEGER >= 5000000)
+// Verilator v5 adds $root wrapper that provides rootp pointer.
+#include "Vcheshire_testharness___024root.h"
+#endif
+
+// #include <fesvr/dtm.h>
+#include <cassert>
+#include <chrono>
+#include <cstring>
+#include <ctime>
+#include <fesvr/elfloader.h>
+#include <fesvr/htif_hexwriter.h>
+#include <getopt.h>
+#include <iomanip>
+#include <iostream>
+#include <signal.h>
+#include <stdio.h>
+#include <string>
+#include <unistd.h>
+
+// This software is heavily based on Rocket Chip
+// Checkout this awesome project:
+// https://github.com/freechipsproject/rocket-chip/
+
+// This is a 64-bit integer to reduce wrap over issues and
+// allow modulus.  You can also use a double, if you wish.
+static vluint64_t main_time = 0;
+int clk_ratio = 2;
+
+static void cycle_start(std::shared_ptr<Vcheshire_testharness> top) {
+    top->rtc_i = 1;
+    top->jtag_tck = 1;
+    for (int i = 0; i < clk_ratio; i++) {
+        top->clk_i = 1;
+        top->rtc_i = 1;
+        printf("tick\n");
+        top->eval();
+        main_time += 2500;
+        top->clk_i = 0;
+        top->rtc_i = 0;
+        top->eval();
+        main_time += 2500;
+    }
+}
+
+static void cycle_end(std::shared_ptr<Vcheshire_testharness> top) {
+    top->rtc_i = 0;
+    for (int i = 0; i < clk_ratio; i++) {
+        top->clk_i = 1;
+        top->rtc_i = 1;
+        top->eval();
+        main_time += 2500;
+        top->clk_i = 0;
+        top->rtc_i = 0;
+        top->eval();
+        main_time += 2500;
+    }
+}
+
+static void wait_cycles(std::shared_ptr<Vcheshire_testharness> top, int cycles) {
+    for (int i = 0; i < cycles; i++) {
+        cycle_start(top);
+        cycle_end(top);
+    }
+}
+
+int main(int argc, char **argv) {
+
+    Verilated::commandArgs(argc, argv);
+    std::shared_ptr<Vcheshire_testharness> top(new Vcheshire_testharness);
+
+    // reset
+    for (int i = 0; i < 10; i++) {
+        top->rst_ni = 0;
+        top->rtc_i = 0;
+        wait_cycles(top, 5);
+    }
+    top->rst_ni = 1;
+
+    top->final();
+
+    return 0;
+}