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hw: Fix iDMA integration
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colluca committed Aug 30, 2024
1 parent 4b13ba8 commit 00cfe17
Showing 1 changed file with 13 additions and 6 deletions.
19 changes: 13 additions & 6 deletions hw/occamy/occamy_soc.sv.tpl
Original file line number Diff line number Diff line change
Expand Up @@ -412,7 +412,14 @@ module ${name}_soc
.change_dw(context, 32, "out_sys_idma_cfg_dw") \
%>\

<% in_sys_idma_mst = soc_wide_xbar.__dict__["in_sys_idma_mst"] %>\
// iDMA master AXI bus
<%
in_sys_idma_mst = soc_wide_xbar.__dict__["in_sys_idma_mst"].copy(name="sys_idma_mst")
in_sys_idma_mst.uw = 1
in_sys_idma_mst.type_prefix = in_sys_idma_mst.emit_struct()
in_sys_idma_mst.declare(context)
in_sys_idma_mst.change_uw(context, soc_wide_xbar.__dict__["in_sys_idma_mst"].uw, "", to=soc_wide_xbar.__dict__["in_sys_idma_mst"])
%>\

// local regbus definition
`REG_BUS_TYPEDEF_ALL(idma_cfg_reg_a${wide_in.aw}_d32, logic [${wide_in.aw-1}:0], logic [31:0], logic [7:0])
Expand Down Expand Up @@ -530,13 +537,13 @@ module ${name}_soc
);

idma_backend_rw_axi #(
.DataWidth ( ${wide_in.dw-1} ),
.AddrWidth ( ${wide_in.aw-1} ),
.UserWidth ( ${wide_in.uw} ),
.AxiIdWidth ( ${wide_in.iw-1} ),
.DataWidth ( ${in_sys_idma_mst.dw} ),
.AddrWidth ( ${in_sys_idma_mst.aw} ),
.UserWidth ( ${in_sys_idma_mst.uw} ),
.AxiIdWidth ( ${in_sys_idma_mst.iw} ),
.NumAxInFlight ( 32'd64 ),
.BufferDepth ( 32'd3 ),
.TFLenWidth ( ${wide_in.aw-1} ),
.TFLenWidth ( ${in_sys_idma_mst.aw} ),
.MemSysDepth ( 32'd16 ),
.CombinedShifter ( 1'b1 ),
.RAWCouplingAvail ( 1'b1 ),
Expand Down

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