multiple fixes

pulp-platform · Feb 26, 2024 · b7cef2f · b7cef2f
1 parent 94046fc
commit b7cef2f
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Showing 8 changed files with 47 additions and 52 deletions.
diff --git a/Bender.lock b/Bender.lock
@@ -15,13 +15,6 @@ packages:
     - common_cells
     - common_verification
     - tech_cells_generic
-  axi_mem_if:
-    revision: 3567273b4f67bd57a81a2a503394a49641bae53a
-    version: 0.2.1
-    source:
-      Git: [email protected]:pulp-platform/axi_mem_if.git
-    dependencies:
-    - axi
   axi_stream:
     revision: 54891ff40455ca94a37641b9da4604647878cc07
     version: 0.1.1
@@ -45,7 +38,7 @@ packages:
     dependencies: []
   idma:
     revision: a80fcace92b1562e7cd76c8615298b5623ba74d2
-    version: null
+    version: 0.6.0-beta
     source:
       Git: [email protected]:pulp-platform/iDMA.git
     dependencies:

diff --git a/Bender.yml b/Bender.yml
@@ -16,12 +16,11 @@ package:
 
 dependencies:
   axi : { git: "[email protected]:pulp-platform/axi.git",                                     version: 0.39.1 }
-  axi_mem_if : { git: [email protected]:pulp-platform/axi_mem_if.git,                         version: 0.2.1  }
   axi_stream: { git: "[email protected]:pulp-platform/axi_stream.git",                        rev: "54891ff"  } # branch: main
   common_verification : { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3  }
   register_interface : { git: "https://github.com/pulp-platform/register_interface.git",   version: 0.4.2  }
   common_cells: { git: "https://github.com/pulp-platform/common_cells.git",                version: 1.32.0 }
-  idma: { git: "[email protected]:pulp-platform/iDMA.git",                                    rev: "a80fcac"  } # branch: cl/idma-eth
+  idma: { git: "[email protected]:pulp-platform/iDMA.git",                                    rev: "a80fcac"  } # branch: main
 
 sources:
   # Source files grouped in levels. Files in level 0 have no dependencies on files in this

diff --git a/README.md b/README.md
@@ -17,7 +17,7 @@ used.
 `pulp-ethernet` is intended for use with https://github.com/pulp-platform/ariane
 (a RISCV Linux-capable soft core).
 
-## Generate iDMA with AXIS support  (Terminal)
+## Generate iDMA
 
 ```
 make eth-idma-gen
@@ -26,12 +26,12 @@ make eth-idma-gen
 ## Compile (Questa)
 
 ```
-make eth-hw-build
+make eth-sim-build
 ```
 
 ## Simulate (Questa)
 ```
-make eth-hw-sim
+make eth-vsim-sim-run
 ```
 
 ### Debugging

diff --git a/rtl/eth_idma_pkg.sv b/rtl/eth_idma_pkg.sv
@@ -1,7 +1,8 @@
-// Copyright 2023 ETH Zurich and University of Bologna.
+// Copyright 2024 ETH Zurich and University of Bologna.
 // Solderpad Hardware License, Version 0.51, see LICENSE for details.
 // SPDX-License-Identifier: SHL-0.51
-
+//
+// Chaoqun Liang <[email protected]>
 
 `include "axi_stream/assign.svh"
 `include "axi_stream/typedef.svh"
@@ -13,13 +14,13 @@
 package eth_idma_pkg;
 
   /// Ethernet reg typedefs
-  parameter  int AW_REGBUS           = 32;
-  localparam int DW_REGBUS           = 32;
-  localparam int unsigned STRB_WIDTH = DW_REGBUS/8;
+  parameter  int unsigned AwRegbus           = 32;    
+  localparam int unsigned DwRegbus           = 32;     
+  localparam int unsigned StrbWidth          = DwRegbus/8;    
 
-  typedef logic [AW_REGBUS-1:0]   reg_bus_addr_t;
-  typedef logic [DW_REGBUS-1:0]   reg_bus_data_t;
-  typedef logic [STRB_WIDTH-1:0]  reg_bus_strb_t;
+  typedef logic [AwRegbus-1:0]   reg_bus_addr_t;
+  typedef logic [DwRegbus-1:0]   reg_bus_data_t;
+  typedef logic [StrbWidth-1:0]  reg_bus_strb_t;
 
   `REG_BUS_TYPEDEF_ALL(reg_bus, reg_bus_addr_t, reg_bus_data_t, reg_bus_strb_t)
 
@@ -29,13 +30,13 @@ package eth_idma_pkg;
   parameter int unsigned AxiIdWidth          = 5;
   parameter int unsigned TFLenWidth          = 32;
 
-  localparam int unsigned StrbWidth     = DataWidth / 8;
+  localparam int unsigned AxiStrbWidth     = DataWidth / 8;
   localparam int unsigned OffsetWidth   = $clog2(StrbWidth);
 
   typedef logic [AddrWidth-1:0]   addr_t;
   typedef logic [AxiIdWidth-1:0]  id_t;
   typedef logic [UserWidth-1:0]   user_t;
-  typedef logic [StrbWidth-1:0]   strb_t;
+  typedef logic [AxiStrbWidth-1:0]   strb_t;
   typedef logic [DataWidth-1:0]   data_t;
   typedef logic [TFLenWidth-1:0]  tf_len_t;
 

diff --git a/rtl/eth_idma_wrap.sv b/rtl/eth_idma_wrap.sv
@@ -50,7 +50,7 @@ module eth_idma_wrap #(
 )(
   input  logic                       clk_i,
   input  logic                       rst_ni,
-  /// Etherent Internal clocks
+  /// Ethernet Internal clocks
   input  logic                       eth_clk_i, 
   input  logic                       eth_clk90_i,
   /// Ethernet: 1000BASE-T RGMII

diff --git a/rtl/eth_top.sv b/rtl/eth_top.sv
@@ -1,4 +1,4 @@
-/// Copyright 2023 ETH Zurich and University of Bologna.
+// Copyright 2024 ETH Zurich and University of Bologna.
 // Solderpad Hardware License, Version 0.51, see LICENSE for details.
 // SPDX-License-Identifier: SHL-0.51
 //

diff --git a/rtl/framing_top.sv b/rtl/framing_top.sv
@@ -1,5 +1,11 @@
-// See LICENSE for license details.
-
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Authors:
+// - Jonathan Kimmitt <[email protected]>
+// - Thiemo Zaugg <[email protected]>
+// - chaoqun Liang <[email protected]>
 
 module framing_top #(
   /// AXI Stream in request struct

diff --git a/target/sim/src/eth_tb.sv b/target/sim/src/eth_tb.sv
@@ -37,14 +37,14 @@ module eth_tb
   import reg_test::*;
 
   /// timing parameters
-  localparam time SYS_TCK       = 8ns;
-  localparam time TCK125        = 8ns;
-  localparam time SYS_TA        = 2ns;
-  localparam time SYS_TT        = 6ns;
+  localparam time SYS_TCK      = 8ns;
+  localparam time TCK125       = 8ns;
+  localparam time SYS_TA       = 2ns;
+  localparam time SYS_TT       = 6ns;
 
   /// regbus
-  localparam int unsigned REG_BUS_DW  = 32;
-  localparam int unsigned REG_BUS_AW  = 32;
+  localparam int unsigned RegBusDw  = 32;
+  localparam int unsigned RegBusAw  = 32;
 
   /// parse error handling caps
   localparam error_cap_e ErrorCap = ErrorHandling ? ERROR_HANDLING : NO_ERROR_HANDLING;
@@ -54,11 +54,10 @@ module eth_tb
   logic       s_clk_125MHz_0;
   logic       s_clk_125MHz_90;
   logic       s_rst_n;
-  logic       done  = 0;
   logic       error_found = 0;
 
-  logic [REG_BUS_DW-1:0] tx_req_ready, tx_rsp_valid;
-  logic [REG_BUS_DW-1:0] rx_req_ready, rx_rsp_valid;
+  logic [RegBusDw-1:0] tx_req_ready, tx_rsp_valid;
+  logic [RegBusAw-1:0] rx_req_ready, rx_rsp_valid;
 
   logic       eth_rxck;
   logic       eth_rxctl;
@@ -85,22 +84,22 @@ module eth_tb
 
   /// -------------------- REG Drivers -----------------------
   typedef reg_test::reg_driver #(
-    .AW(REG_BUS_AW),
-    .DW(REG_BUS_DW),
+    .AW(RegBusAw),
+    .DW(RegBusDw),
     .TT(SYS_TT),
     .TA(SYS_TA)
   ) reg_bus_drv_t;
 
   REG_BUS #(
-    .DATA_WIDTH(REG_BUS_DW),
-    .ADDR_WIDTH(REG_BUS_AW)
+    .DATA_WIDTH(RegBusDw),
+    .ADDR_WIDTH(RegBusAw)
   )  reg_bus_tx (
     .clk_i(s_clk)
   );
 
   REG_BUS #(
-    .DATA_WIDTH(REG_BUS_DW),
-    .ADDR_WIDTH(REG_BUS_AW)
+    .DATA_WIDTH(RegBusDw),
+    .ADDR_WIDTH(RegBusAw)
   )  reg_bus_rx (
     .clk_i(s_clk)
   );
@@ -281,24 +280,21 @@ module eth_tb
 
     // ------------------------ BEGINNING OF SIMULATION ------------------------
 
-   initial begin
-     while (!done) begin
-      s_clk_125MHz_0 <= 1;
-      #(TCK125/2);
-      s_clk_125MHz_0 <= 0;
-      #(TCK125/2);
-     end
-   end
+    clk_rst_gen #(
+    .ClkPeriod    ( TCK125  ),
+    .RstClkCycles ( 5       )
+  ) i_clk_rst_125_gen (
+      .clk_o  ( s_clk_125MHz_0  ),
+      .rst_no (                 )
+  );
 
   initial begin
-    while (!done) begin
       s_clk_125MHz_90 <= 0;
       #(TCK125/4);
       s_clk_125MHz_90 <= 1;
       #(TCK125/2);
       s_clk_125MHz_90 <= 0;
        #(TCK125/4);
-    end
    end
 
    initial begin