Merge pull request #2 from pulp-platform/aottaviano/bufferless-design

treewide: Upstream codebase for buffer-less design

Bender.lock

@@ -1,4 +1,11 @@
 packages:
+  apb:
+    revision: 77ddf073f194d44b9119949d2421be59789e69ae
+    version: 0.2.4
+    source:
+      Git: https://github.com/pulp-platform/apb.git
+    dependencies:
+    - common_cells
   axi:
     revision: fccffb5953ec8564218ba05e20adbedec845e014
     version: 0.39.1
@@ -15,6 +22,13 @@ packages:
       Git: [email protected]:pulp-platform/axi_mem_if.git
     dependencies:
     - axi
+  axi_stream:
+    revision: 472751f550e3918215603e21734fe0ece3c66f79
+    version: null
+    source:
+      Git: [email protected]:pulp-platform/axi_stream.git
+    dependencies:
+    - common_cells
   common_cells:
     revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f
     version: 1.32.0
@@ -29,6 +43,15 @@ packages:
     source:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
+  register_interface:
+    revision: 146501d80052b61475cdc333d3aab4cd769fd5dc
+    version: 0.3.9
+    source:
+      Git: https://github.com/pulp-platform/register_interface.git
+    dependencies:
+    - apb
+    - axi
+    - common_cells
   tech_cells_generic:
     revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
     version: 0.2.13

Bender.yml

@@ -3,41 +3,47 @@ package:
 
   authors:
     - "Alessandro Ottaviano <[email protected]>" # current maintainer
+    - "Thomas Benz <[email protected]>"
+    - "Thiemo Zaugg <[email protected]>"
+    - "Mattia Girotti"
+    - "Alice Afrangoli"
+    - "Chaoqun Liang <[email protected]>"
+    - "Davide Rossi <[email protected]>"
 
 dependencies:
   axi_mem_if : { git: [email protected]:pulp-platform/axi_mem_if.git, version: 0.2.1 }
   axi : { git: "[email protected]:pulp-platform/axi.git", version: 0.39.1 }
   common_verification : { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 }
+  register_interface : { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8 }
+  common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 }
+  axi_stream: { git: "[email protected]:pulp-platform/axi_stream.git", rev: "472751f550e3918215603e21734fe0ece3c66f79" }
 
 sources:
   # Source files grouped in levels. Files in level 0 have no dependencies on files in this
   # package. Files in level 1 only depend on files in level 0, files in level 2 on files in
   # levels 1 and 0, etc. Files within a level are ordered alphabetically.
   # Level 0
-  - rtl/axis_async_fifo.sv
+  - gen/eth_framing_reg_pkg.sv
+  - gen/eth_framing_reg_top.sv
   - rtl/axis_gmii_rx.sv
   - rtl/axis_gmii_tx.sv
-  - rtl/mem_wrap_tx.sv
-  - rtl/dualmem_widen8.sv
-  - rtl/dualmem_widen.sv
+  # Level 1
   - rtl/eth_mac_1g_rgmii_fifo.sv
   - rtl/eth_mac_1g_rgmii.sv
   - rtl/eth_mac_1g.sv
-  - rtl/eth_rgmii.sv
-  - rtl/framing_top.sv
   - rtl/iddr.sv
   - rtl/oddr.sv
   - rtl/rgmii_core.sv
   - rtl/rgmii_lfsr.sv
   - rtl/rgmii_phy_if.sv
   - rtl/rgmii_soc.sv
   - rtl/ssio_ddr_in.sv
-  - rtl/mem_wrap_rx.sv
-  - rtl/eth_rgmii_pkg.sv
-  - rtl/eth_rgmii_synth.sv
+  # Level 2
+  - rtl/framing_top.sv
+  - rtl/eth_top_pkg.sv
+  - rtl/eth_top.sv
+  - target/synth/eth_top_synth.sv
 
   - target: test
     files:
-      - rtl/simple_dual_two_clocks.v
       - target/sim/src/eth_tb.sv
-      - target/sim/src/fixture_eth.sv

Makefile

@@ -1,6 +1,16 @@
-# Copyright 2023 ETH Zurich and University of Bologna.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
+# Copyright 2023 ETH Zurich
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
 
 # Author: Alessandro Ottaviano <[email protected]>
 

eth.mk

@@ -1,6 +1,16 @@
-# Copyright 2023 ETH Zurich and University of Bologna.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
+# Copyright 2023 ETH Zurich
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
 #
 # Author: Alessandro Ottaviano <[email protected]>
 
@@ -29,7 +39,7 @@ endif
 ######################
 
 ETH_NONFREE_REMOTE ?= [email protected]:pulp-restricted/pulp-ethernet-nonfree.git
-ETH_NONFREE_COMMIT ?= 93c43bf
+ETH_NONFREE_COMMIT ?= cd8dcd3
 
 eth-nonfree-init:
 	git clone $(ETH_NONFREE_REMOTE) $(ETH_ROOT)/nonfree

gen/Makefile

@@ -0,0 +1,41 @@
+# Copyright 2023 ETH Zurich
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# Author: Robert Balas <[email protected]>
+
+# Generate C header and SystemVerilog files
+
+REGTOOL ?= regtool.py
+
+SRCS = eth_framing_reg_top.sv eth_framing_reg_pkg.sv
+
+all: srcs headers
+
+srcs: $(SRCS)
+
+eth_framing_reg_top.sv: eth_framing_regs.hjson
+	$(REGTOOL) -r $< -t .
+
+headers: eth_framing.h
+
+eth_framing.h: eth_framing_regs.hjson
+	$(REGTOOL) --cdefines $< > $@
+
+.PHONY: install
+install:
+	cp $(SRCS) ../rtl
+
+.PHONY: clean
+clean:
+	rm $(SRCS)

gen/eth_framing.h

@@ -0,0 +1,37 @@
+// Generated register defines for eth_framing
+
+#ifndef _ETH_FRAMING_REG_DEFS_
+#define _ETH_FRAMING_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Register width
+#define ETH_FRAMING_PARAM_REG_WIDTH 32
+
+// Configures the lower 4 bytes of the devices MAC address
+#define ETH_FRAMING_CONFIG0_REG_OFFSET 0x0
+
+// Configures the: upper 2 bytes of the devices MAC address, promiscuous
+// flag, MDIO interface
+#define ETH_FRAMING_CONFIG1_REG_OFFSET 0x4
+#define ETH_FRAMING_CONFIG1_UPPER_MAC_ADDRESS_MASK 0xffff
+#define ETH_FRAMING_CONFIG1_UPPER_MAC_ADDRESS_OFFSET 0
+#define ETH_FRAMING_CONFIG1_UPPER_MAC_ADDRESS_FIELD \
+  ((bitfield_field32_t) { .mask = ETH_FRAMING_CONFIG1_UPPER_MAC_ADDRESS_MASK, .index = ETH_FRAMING_CONFIG1_UPPER_MAC_ADDRESS_OFFSET })
+#define ETH_FRAMING_CONFIG1_PROMISCUOUS_BIT 16
+#define ETH_FRAMING_CONFIG1_PHY_MDCLK_BIT 17
+#define ETH_FRAMING_CONFIG1_PHY_MDIO_O_BIT 18
+#define ETH_FRAMING_CONFIG1_PHY_MDIO_OE_BIT 19
+
+// The FCS TX status
+#define ETH_FRAMING_CONFIG2_REG_OFFSET 0x8
+
+// The FCS RX status
+#define ETH_FRAMING_CONFIG3_REG_OFFSET 0xc
+
+#ifdef __cplusplus
+}  // extern "C"
+#endif
+#endif  // _ETH_FRAMING_REG_DEFS_
+// End generated register defines for eth_framing

gen/eth_framing_reg_pkg.sv

@@ -0,0 +1,83 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package eth_framing_reg_pkg;
+
+  // Address widths within the block
+  parameter int BlockAw = 4;
+
+  ////////////////////////////
+  // Typedefs for registers //
+  ////////////////////////////
+
+  typedef struct packed {
+    logic [31:0] q;
+  } eth_framing_reg2hw_config0_reg_t;
+
+  typedef struct packed {
+    struct packed {
+      logic [15:0] q;
+    } upper_mac_address;
+    struct packed {
+      logic        q;
+    } promiscuous;
+    struct packed {
+      logic        q;
+    } phy_mdclk;
+    struct packed {
+      logic        q;
+    } phy_mdio_o;
+    struct packed {
+      logic        q;
+    } phy_mdio_oe;
+  } eth_framing_reg2hw_config1_reg_t;
+
+  typedef struct packed {
+    logic [31:0] d;
+    logic        de;
+  } eth_framing_hw2reg_config2_reg_t;
+
+  typedef struct packed {
+    logic [31:0] d;
+    logic        de;
+  } eth_framing_hw2reg_config3_reg_t;
+
+  // Register -> HW type
+  typedef struct packed {
+    eth_framing_reg2hw_config0_reg_t config0; // [51:20]
+    eth_framing_reg2hw_config1_reg_t config1; // [19:0]
+  } eth_framing_reg2hw_t;
+
+  // HW -> register type
+  typedef struct packed {
+    eth_framing_hw2reg_config2_reg_t config2; // [65:33]
+    eth_framing_hw2reg_config3_reg_t config3; // [32:0]
+  } eth_framing_hw2reg_t;
+
+  // Register offsets
+  parameter logic [BlockAw-1:0] ETH_FRAMING_CONFIG0_OFFSET = 4'h 0;
+  parameter logic [BlockAw-1:0] ETH_FRAMING_CONFIG1_OFFSET = 4'h 4;
+  parameter logic [BlockAw-1:0] ETH_FRAMING_CONFIG2_OFFSET = 4'h 8;
+  parameter logic [BlockAw-1:0] ETH_FRAMING_CONFIG3_OFFSET = 4'h c;
+
+  // Register index
+  typedef enum int {
+    ETH_FRAMING_CONFIG0,
+    ETH_FRAMING_CONFIG1,
+    ETH_FRAMING_CONFIG2,
+    ETH_FRAMING_CONFIG3
+  } eth_framing_id_e;
+
+  // Register width information to check illegal writes
+  parameter logic [3:0] ETH_FRAMING_PERMIT [4] = '{
+    4'b 1111, // index[0] ETH_FRAMING_CONFIG0
+    4'b 0111, // index[1] ETH_FRAMING_CONFIG1
+    4'b 1111, // index[2] ETH_FRAMING_CONFIG2
+    4'b 1111  // index[3] ETH_FRAMING_CONFIG3
+  };
+
+endpackage
+