Merge pull request #15 from ShrreyaSingh/disassembler_changes

Disassembler changes for instruction name (auipc, jal, jalr, lui)

CHANGELOG.md

@@ -2,6 +2,9 @@
 
 This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+## [0.6.6] - 2021-08-03
+- Bug fix for error while decoding instruction name
+
 ## [0.6.5] - 2021-07-14
 - Bug fix for error while generating Data Propagation Report.
 

riscv_isac/__init__.py

@@ -4,4 +4,4 @@
 
 __author__ = """InCore Semiconductors Pvt Ltd"""
 __email__ = '[email protected]'
-__version__ = '0.6.5'
+__version__ = '0.6.6'

riscv_isac/coverage.py

@@ -23,7 +23,7 @@
 from collections.abc import MutableMapping
 
 
-unsgn_rs1 = ['sw','sd','sh','sb','ld','lw','lwu','lh','lhu','lb', 'lbu','flw','fld','fsw','fsd'\
+unsgn_rs1 = ['sw','sd','sh','sb','ld','lw','lwu','lh','lhu','lb', 'lbu','flw','fld','fsw','fsd',\
         'bgeu', 'bltu', 'sltiu', 'sltu','c.lw','c.ld','c.lwsp','c.ldsp',\
         'c.sw','c.sd','c.swsp','c.sdsp','mulhu','divu','remu','divuw',\
         'remuw','aes64ds','aes64dsm','aes64es','aes64esm','aes64ks2',\
@@ -770,6 +770,7 @@ def compute(trace_file, test_name, cgf, parser_name, decoder_name, detailed, xle
         if instr is None:
             continue
         instrObj = (decoder.decode(instrObj_temp = instrObj_temp))[0]
+        logger.debug(instrObj)
         rcgf = compute_per_line(instrObj, cgf, xlen,
                         addr_pairs, sig_addrs)
 

riscv_isac/plugins/internaldecoder.py

@@ -63,6 +63,7 @@ def lui(self, instrObj):
         rd = ((instr & self.RD_MASK) >> 7, 'x')
         instrObj.rd = rd
         instrObj.imm = imm
+        instrObj.instr_name = "lui"
         return instrObj
 
     def auipc(self, instrObj):
@@ -71,6 +72,7 @@ def auipc(self, instrObj):
         rd = ((instr & self.RD_MASK) >> 7, 'x')
         instrObj.rd = rd
         instrObj.imm = imm
+        instrObj.instr_name = "auipc"
         return instrObj
 
     def jal(self, instrObj):
@@ -84,6 +86,7 @@ def jal(self, instrObj):
         rd = ((instr & self.RD_MASK) >> 7, 'x')
         instrObj.imm = imm
         instrObj.rd = rd
+        instrObj.instr_name = "jal"
         return instrObj
 
     def jalr(self, instrObj):
@@ -95,6 +98,7 @@ def jalr(self, instrObj):
         instrObj.rd = rd
         instrObj.rs1 = rs1
         instrObj.imm = imm
+        instrObj.instr_name = "jalr"
         return instrObj
 
     def branch_ops(self, instrObj):

riscv_isac/requirements.txt

@@ -1,5 +1,6 @@
 click
 ruamel.yaml>=0.16.0
+pyyaml
 pyelftools==0.26
 colorlog
 pytest

setup.cfg

@@ -1,5 +1,5 @@
 [bumpversion]
-current_version = 0.6.5
+current_version = 0.6.6
 commit = True
 tag = True
 

setup.py

@@ -26,7 +26,7 @@ def read_requires():
 
 setup(
     name='riscv_isac',
-    version='0.6.5',
+    version='0.6.6',
     description="RISC-V ISAC",
     long_description=readme + '\n\n',
     classifiers=[