formating fixes

cfi_backward.adoc

@@ -409,14 +409,14 @@ register, e.g., `x1` and/or `x5`, from arbitrary modification by not emitting
 unsafe code sequences.
 ====
 
+<<<
+
 [NOTE]
 ====
 Storing the return address on both stacks preserves the call stack layout and
 the ABI, while also allowing for the detection of corruption of the return
-address on the regular stack.
-
-The prologue and epilogue of a non-leaf function that uses shadow stacks is as
-follows:
+address on the regular stack. The prologue and epilogue of a non-leaf function
+that uses shadow stacks is as follows:
 
 [listing]
 ----
@@ -517,16 +517,16 @@ jump to the return address.
         c.sd x1,(sp)     # on data stack
         c.sspush x1      # push link register x1 on shadow stack
          :
-         :
         c.ld x5,(sp)     # pop link register x5 from data stack
         c.addi sp,sp,8
-        c.sspopchk x5    # compare link register x5 to shadow
-                         # return address; faults if not same
+        c.sspopchk x5    # fault if x5 not equal to shadow return address
         c.jr x5
 ----
 
 ====
 
+<<<
+
 [NOTE]
 ====
 Store-to-load forwarding is a common technique employed by high-performance
@@ -591,6 +591,8 @@ Operating systems and runtimes must not locate shadow stacks at address 0 to
 assist with the use of such code sequences.
 ====
 
+<<<
+
 [NOTE]
 ====
 A common operation performed on stacks is to unwind them to support constructs
@@ -639,6 +641,8 @@ back_cfi_not_active:
 }
 ====
 
+<<<
+
 [[SSAMOSWAP]]
 === Atomic Swap from a shadow stack location
 
@@ -696,6 +700,8 @@ consistency semantics, using the `aq` and `rl` bits, to help implement
 multiprocessor synchronization. The memory operation performed by an
 `SSAMOSWAP`, has acquire semantics if `aq=1` and has release semantics if `rl=1`.
 
+<<<
+
 [NOTE]
 ====
 Stack switching is a common operation in user programs as well as supervisor
@@ -746,6 +752,8 @@ memory location operated on by `SSAMOSWAP` is not required, `rd` can be set to
 `x0`.
 ====
 
+<<<
+
 [[SSMP]]
 === Shadow Stack Memory Protection
 

cfi_forward.adoc

@@ -111,6 +111,8 @@ An indirect branch using `JALR`, `C.JALR`, or `C.JR` with `rs1` as `x7` is
 termed a software guarded branch. Such branches do not need to land on a
 `LPAD` instruction and thus do not set `ELP` to `LP_EXPECTED`.
 
+<<<
+
 [NOTE]
 ====
 When the register source is a link register and the register destination is `x0`
@@ -159,6 +161,8 @@ in bits 31:12 of the `x7` register, then a software-check exception (cause=18)
 with `__x__tval` set to "landing pad fault (code=2)" is raised else the `ELP` is
 updated to `NO_LP_EXPECTED`.
 
+<<<
+
 [NOTE]
 ====
 The tracking of `ELP` and the requirement for a landing pad instruction
@@ -181,6 +185,8 @@ not a valid landing pad or may use an alternate register allocation to prevent
 the accidental landing pad.
 ====
 
+<<<
+
 === Zicfilp CSRs
 
 This section specifies the CSR state of the Zicfilp extension.