Cleanup CSR comments

model/riscv_csr_begin.sail

@@ -12,20 +12,9 @@ val csr_name_map : csreg <-> string
 
 scattered mapping csr_name_map
 
-// TODO: These csr_name_map definitions should be moved to the files
-// corresponding to their extensions rather than all be here.
-
 val csr_name : csreg -> string
 overload to_str = {csr_name}
 
-/* Extensions may want to add additional CSR registers to the CSR address map.
- * These scattered functions support access to such registers.
- *
- * The default implementation provides access to the CSRs added by the 'N'
- * extension.
- */
-
-
 /* returns whether a CSR exists
  */
 val is_CSR_defined : (csreg) -> bool

model/riscv_insts_zicsr.sail

@@ -8,7 +8,6 @@
 
 /* ****************************************************************** */
 /* This file specifies the instructions in the 'Zicsr' extension.     */
-
 /* ****************************************************************** */
 union clause ast = CSR  : (csreg, regidx, regidx, bool, csrop)
 
@@ -21,10 +20,6 @@ mapping encdec_csrop : csrop <-> bits(2) = {
 mapping clause encdec = CSR(csr, rs1, rd, is_imm, op)
   <-> csr @ rs1 @ bool_bits(is_imm) @ encdec_csrop(op) @ rd @ 0b1110011
 
-// TODO: These read/write_CSR definitions should be moved to the files
-// corresponding to their extensions rather than all be here.
-
-
 function clause execute CSR(csr, rs1, rd, is_imm, op) = {
   let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1);
   let isWrite : bool = match op {

model/riscv_sys_control.sail

@@ -13,13 +13,6 @@
 function csrAccess(csr : csreg) -> csrRW = csr[11..10]
 function csrPriv(csr : csreg) -> priv_level = csr[9..8]
 
-// TODO: These is_CSR_defined definitions should be moved to the files
-// corresponding to their extensions rather than all be here.
-
-
-
-
-
 val check_CSR_access : (csrRW, priv_level, Privilege, bool) -> bool
 function check_CSR_access(csrrw, csrpr, p, isWrite) =
     not(isWrite == true & csrrw == 0b11)  /* read/write */