Successful extmem for data test, cache bug fixes

dev/hdl/main.sv

@@ -37,22 +37,32 @@ module main#(
     // A 32-bit quantity of randomness.
     input  logic[31:0]  randomness,
 
+    // Additional MMIO bus.
+    boa_mem_bus.CPU     xmp_bus,
+    // External program bus.
+    boa_mem_bus.CPU     xmi_bus,
+    // External data bus.
+    boa_mem_bus.CPU     xmd_bus,
+
     // Power management unit interface.
-    pmu_bus.CPU pmb
+    pmu_bus.CPU         pmb
 );
     `include "boa_fileio.svh"
 
     // Memory buses.
     boa_mem_bus pbus();
     boa_mem_bus dbus();
-    boa_mem_bus mux_a_bus[2]();
-    boa_mem_bus mux_b_bus[3]();
-    boa_mem_bus#(.alen(12)) peri_bus[13]();
+    boa_mem_bus mux_a_bus[3]();
+    boa_mem_bus mux_b_bus[4]();
+    boa_mem_bus#(.alen(12)) peri_bus[14]();
 
     // Program ROM.
     dp_block_ram#(10, rom_file, 1) rom(clk, mux_a_bus[0], mux_b_bus[0]);
     // RAM.
     dp_block_ram#(14, "", 0) ram(clk, mux_a_bus[1], mux_b_bus[1]);
+    // External memory.
+    boa_mem_connector xmi_conn(xmi_bus, mux_a_bus[2]);
+    boa_mem_connector xmd_conn(xmd_bus, mux_b_bus[2]);
 
     // UART.
     logic rx_full, tx_empty;
@@ -78,12 +88,14 @@ module main#(
     boa_peri_pwm#(.addr('h4e0)) pwm6gen(clk, clk, rst, peri_bus[4+6], gpio_ext_sig[6]);
     boa_peri_pwm#(.addr('h4f0)) pwm7gen(clk, clk, rst, peri_bus[4+7], gpio_ext_sig[7]);
     // Is simulator?
-    boa_peri_readable#(.addr('hffc)) is_sim(clk, rst, peri_bus[12], is_simulator);
+    boa_peri_readable#(.addr('h310)) is_sim(clk, rst, peri_bus[12], is_simulator);
+    // External MMIO bus.
+    boa_mem_connector xmp_conn(xmp_bus, peri_bus[13]);
 
     // Memory interconnects.
-    boa_mem_mux#(.mems(2)) mux_a(clk, rst, pbus, mux_a_bus, {32'h40001000, 32'h40010000},               {12, 16});
-    boa_mem_mux#(.mems(3)) mux_b(clk, rst, dbus, mux_b_bus, {32'h40001000, 32'h40010000, 32'h80000000}, {12, 16, 12});
-    boa_mem_overlay#(.mems(13)) ovl(mux_b_bus[2], peri_bus);
+    boa_mem_mux#(.mems(3)) mux_a(clk, rst, pbus, mux_a_bus, {32'h4000_1000, 32'h4001_0000, 32'h8000_0000},                {12, 16, 24});
+    boa_mem_mux#(.mems(4)) mux_b(clk, rst, dbus, mux_b_bus, {32'h4000_1000, 32'h4001_0000, 32'h8000_0000, 32'h2000_0000}, {12, 16, 24, 12});
+    boa_mem_overlay#(.mems(14)) ovl(mux_b_bus[3], peri_bus);
 
     // CPU.
     logic[31:16] irq;

dev/hdl/mem/cache.sv

@@ -204,20 +204,21 @@ module boa_cache#(
 
     // Next address in sequential extmem access.
     logic[alen-1:2]             xm_next_addr;
-    assign xm_next_addr[alen-1:agrain]              = xm_addr[alen-1:agrain];
+    assign xm_next_addr[alen-1:agrain]              = xm_bus.addr[alen-1:agrain];
     assign xm_next_addr[agrain-1:2]                 = xm_addr[agrain-1:2] + 1;
     // Next address in sequential cachemem access.
     logic[lwidth+lswidth-1:0]   cm_next_addr;
-    assign cm_next_addr[lwidth+lswidth-1:lswidth]   = cm_addr[lwidth+lswidth-1:lswidth];
+    assign cm_next_addr[lwidth+lswidth-1:lswidth]   = cache_raddr[lwidth+lswidth-1:lswidth];
     assign cm_next_addr[lswidth-1:0]                = cm_addr[lswidth-1:0] + 1;
     // Initial extmem address for extmem to cache copy.
     logic[alen-1:2]             xm_init_raddr;
     assign xm_init_raddr[alen-1:agrain]             = bus.addr[alen-1:agrain];
     assign xm_init_raddr[agrain-1:2]                = 0;
     // Initial extmem address for cache to extmem copy.
     logic[alen-1:2]             xm_init_waddr;
-    assign xm_init_waddr[alen-1:agrain]             = ab_addr[alen-1:agrain];
-    assign xm_init_waddr[agrain-1:2]                = 0;
+    assign xm_init_waddr[alen-1:tgrain]             = rtag_addr[rtag_wnext][alen-1:tgrain];
+    assign xm_init_waddr[tgrain-1:lswidth]          = ab_addr[tgrain-1:lswidth];
+    assign xm_init_waddr[lswidth-1:2]               = 0;
     // Initial cache address for cache to extmem copy.
     logic[lwidth+lswidth-1:0]   cm_init_raddr;
     assign cm_init_raddr[lwidth+lswidth-1:lswidth]  = bus.addr[alen-1:agrain];
@@ -240,16 +241,16 @@ module boa_cache#(
             cache_to_xm <= 0;
             xm_addr     <= (xm_addr[agrain-1:2] != 0) ? xm_next_addr : xm_init_raddr;
             cm_addr     <= cm_next_addr;
-            xm_paddr    <= xm_addr;
-            cm_paddr    <= cm_addr;
+            xm_paddr    <= xm_bus.addr;
+            cm_paddr    <= cache_raddr;
         end else if (cache_to_xm) begin
             // Flushing a dirty cache line.
             xm_to_cache <= 0;
             cache_to_xm <= cm_addr[lswidth-1:0] != 0;
             xm_addr     <= xm_next_addr;
             cm_addr     <= (cm_addr[lswidth-1:0] != 0) ? cm_next_addr : cm_init_raddr;
-            xm_paddr    <= xm_addr;
-            cm_paddr    <= cm_addr;
+            xm_paddr    <= xm_bus.addr;
+            cm_paddr    <= cache_raddr;
             xm_pwdata   <= xm_bus.wdata;
         end else if ((ab_re || ab_we) && !tag_valid) begin
             // Non-resident access.
@@ -258,17 +259,17 @@ module boa_cache#(
             xm_way      <= rtag_wnext;
             xm_addr     <= rtag_dirty[rtag_wnext] ? xm_init_waddr : xm_next_addr;
             cm_addr     <= rtag_dirty[rtag_wnext] ? cm_next_addr  : cm_init_waddr;
-            xm_paddr    <= xm_addr;
-            cm_paddr    <= cm_addr;
+            xm_paddr    <= xm_bus.addr;
+            cm_paddr    <= cache_raddr;
         end else begin
             // Cache is idle.
             xm_to_cache <= 0;
             cache_to_xm <= 0;
             xm_way      <= 'bx;
             xm_addr     <= xm_init_raddr;
             cm_addr     <= cm_init_raddr;
-            xm_paddr    <= xm_addr;
-            cm_paddr    <= cm_addr;
+            xm_paddr    <= xm_bus.addr;
+            cm_paddr    <= cache_raddr;
         end
     end
 

hdl/modules/boa_memory.sv

@@ -35,6 +35,19 @@ interface boa_mem_bus#(
     modport MEM (output ready, rdata, input re, we, addr, wdata);
 endinterface
 
+// Boa memory bus connector.
+module boa_mem_connector(
+    boa_mem_bus.CPU cpu,
+    boa_mem_bus.MEM mem
+);
+    assign cpu.re       = mem.re;
+    assign cpu.we       = mem.we;
+    assign cpu.addr     = mem.addr;
+    assign cpu.wdata    = mem.wdata;
+    assign mem.ready    = cpu.ready;
+    assign mem.rdata    = cpu.rdata;
+endmodule
+
 
 
 // Boa memory overlay.

prog/common/ld/memory_layout.ld

@@ -5,13 +5,17 @@ __start_rom     = 0x40001000;
 __stop_rom      = 0x40002000;
 __start_sram    = 0x40010000;
 __stop_sram     = 0x40020000;
-__start_peri    = 0x80000000;
-__stop_peri     = 0x80001000;
+__start_peri    = 0x20000000;
+__stop_peri     = 0x20001000;
+__start_xip     = 0x80000000;
+__stop_xip      = 0x80800000;
+__start_extram  = 0x80800000;
+__stop_extram   = 0x81000000;
 __start_cpummio = 0xff000000;
 __mtime         = __start_cpummio;
 __mtimecmp      = __start_cpummio + 8;
 
-__is_simulator_base = __start_peri + 0xffc;
+__is_simulator_base = __start_peri + 0x310;
 
 __uart0_base = __start_peri + 0x000;
 __pmu_base   = __start_peri + 0x100;

prog/test/src/main.c

@@ -33,21 +33,19 @@ void main() {
     // Set up interrupts.
     asm("csrs mie, %0" ::"r"(0x00020000));
     asm("csrsi mstatus, 8");
-    while (!done);
-    done = false;
-    print("RNG test:\n");
-    putx(RNG, 8);
-    putc('\n');
-    putx(RNG, 8);
-    putc('\n');
-    putx(RNG, 8);
-    putc('\n');
-    putx(RNG, 8);
-    putc('\n');
-    putx(RNG, 8);
-    putc('\n');
+    while (!done)
+        ;
+    done                             = false;
+    *(uint32_t volatile *)0x80800000 = 0xdeadbeef;
+    *(uint32_t volatile *)0x80800010 = 0xf00dbabe;
+    *(uint32_t volatile *)0x80801000 = 0xbaadf00d;
+    *(uint32_t volatile *)0x80802000 = 0xcafebabe;
+    uint32_t x                       = *(uint32_t volatile *)0x80800000;
+    putx(x, 8);
+    print("\n");
     print("Hello, what's your name?\n> ");
-    while (!done);
+    while (!done)
+        ;
     print("Hello, ");
     print((char const *)rxbuf);
     print("!\nYour name is ");

sim/dev/hdl/raw_sram.sv

@@ -0,0 +1,40 @@
+
+// Copyright © 2024, Julian Scheffers, see LICENSE for more information
+
+`timescale 1ns/1ps
+
+
+
+// Simulated zero-latency synchronous SRAM.
+module raw_sram#(
+    // Address width of the SRAM.
+    parameter  alen  = 8,
+    // Storage depth.
+    localparam depth = 1 << alen
+)(
+    // Write clock.
+    input  logic            clk,
+
+    // Read enable.
+    input  logic            re,
+    // Write enable.
+    input  logic            we,
+    // Address.
+    input  logic[alen-1:0]  addr,
+    // Write data.
+    input  logic[7:0]       wdata,
+    // Read data.
+    output logic[7:0]       rdata
+);
+    // Data storage.
+    logic[7:0]  storage[depth];
+
+    // Read access logic.
+    assign rdata = re && !we ? storage[addr] : 'bz;
+    // Write access logic.
+    always @(posedge clk) begin
+        if (we) begin
+            storage[addr] <= wdata;
+        end
+    end
+endmodule

sim/dev/hdl/top.sv

@@ -11,31 +11,73 @@ module top(
     input  logic rx
 );
     `include "boa_fileio.svh"
-    logic[1:0] rst = 3;
+    logic rst = 1;
     logic rtc_clk;
+    param_clk_div#(10, 1) rtc_div(clk, rtc_clk);
+
+    localparam xm_alen = 19;
+
+    // Bus definitions.
     logic[31:0]  gpio_out;
     logic[31:0]  gpio_oe;
     logic[31:0]  gpio_in;
     assign gpio_in = gpio_out;
-    param_clk_div#(10, 1) rtc_div(clk, rtc_clk);
-    pmu_bus pmb();
     logic[31:0] randomness = $urandom();
+    boa_mem_bus#(12) xmp_bus();
+    boa_mem_bus#(24) xmi_bus();
+    boa_mem_bus#(24) xmd_bus();
+    pmu_bus pmb();
+
+    // Main microcontroller device.
     main#(
         .rom_file({boa_parentdir(`__FILE__), "/../obj_dir/rom.mem"}),
         .uart_buf(8192),
         .uart_div(4),
         .is_simulator(1)
     ) main (
-        clk, rtc_clk, rst!=0,
+        clk, rtc_clk, rst,
         tx, rx,
         gpio_out, gpio_oe, gpio_in,
         randomness,
+        xmp_bus, xmi_bus, xmd_bus,
         pmb
     );
+
+    // Additional peripherals.
+    // Extmem size device.
+    boa_peri_readable#('h800) xm_size(clk, rst, xmp_bus, 32'b1 << xm_alen);
+
+    // Simulated external SRAM.
+    logic               sram_re;
+    logic               sram_we;
+    logic[xm_alen-1:0]  sram_addr;
+    logic[7:0]          sram_wdata;
+    logic[7:0]          sram_rdata;
+    raw_sram#(xm_alen) sram(clk, sram_re, sram_we, sram_addr, sram_wdata, sram_rdata);
+    boa_mem_bus sram_bus();
+    boa_extmem_sram#(xm_alen) sram_ctl(clk, rst, sram_bus, sram_re, sram_we, sram_addr, sram_wdata, sram_rdata);
+
+    // Extmem dcache.
+    boa_cache#(
+        xm_alen
+    ) dcache (
+        clk, rst,
+        0, 0, 0, 0,
+        0, 0,
+        xmd_bus,
+        sram_bus
+    );
+
+    // Not any extmem prog for now.
+    assign xmi_bus.ready = 1;
+    assign xmi_bus.rdata = 32'hffff_ffff;
+
     always @(posedge clk) begin
+        // Create new randomness.
         randomness <= $urandom();
+        // Power management bus.
         if (pmb.shdn) begin $display("PMU poweroff"); $finish; end
-        if (pmb.rst) rst <= 3;
-        else if (rst) rst <= rst - 1;
+        if (pmb.rst) rst <= 1;
+        else if (rst) rst <= 0;
     end
 endmodule