smhc: add is cleared functions and several unit test cases

src/ccu.rs

@@ -1263,6 +1263,120 @@ mod tests {
         val = val.gate_mask();
         assert_eq!(val.0, 0x00000000);
     }
-    // TODO structure read/write function unit tests.
-    // Please refer to this link while implementing: https://github.com/rustsbi/bouffalo-hal/blob/6ee8ebf5fde184a68f4c3d5a1b7838dbbc7bfdd3/bouffalo-hal/src/i2c.rs#L902
+
+    #[test]
+    fn struct_uart_bgr_functions() {
+        let mut val = super::UartBusGating(0x0);
+
+        val = val.gate_pass::<0>();
+        assert_eq!(val.0, 0x00000001);
+
+        val = val.gate_mask::<0>();
+        assert_eq!(val.0, 0x00000000);
+
+        val = val.deassert_reset::<0>();
+        assert_eq!(val.0, 0x00010000);
+
+        val = val.assert_reset::<0>();
+        assert_eq!(val.0, 0x00000000);
+
+        val = val.gate_pass::<1>();
+        assert_eq!(val.0, 0x00000002);
+
+        val = val.gate_mask::<1>();
+        assert_eq!(val.0, 0x00000000);
+
+        val = val.deassert_reset::<1>();
+        assert_eq!(val.0, 0x00020000);
+
+        val = val.assert_reset::<1>();
+        assert_eq!(val.0, 0x00000000);
+    }
+
+    #[test]
+    fn struct_spi_clock_functions() {
+        let mut val = super::SpiClock(0x0);
+
+        for i in 0..5 as u8 {
+            let cs_tmp = match i {
+                0x0 => super::SpiClockSource::Hosc,
+                0x1 => super::SpiClockSource::PllPeri1x,
+                0x2 => super::SpiClockSource::PllPeri2x,
+                0x3 => super::SpiClockSource::PllAudio1Div2,
+                0x4 => super::SpiClockSource::PllAudio1Div5,
+                _ => unreachable!(),
+            };
+
+            let val_tmp = match i {
+                0x0 => 0x00000000,
+                0x1 => 0x01000000,
+                0x2 => 0x02000000,
+                0x3 => 0x03000000,
+                0x4 => 0x04000000,
+                _ => unreachable!(),
+            };
+
+            val = val.set_clock_source(cs_tmp);
+            assert_eq!(val.clock_source(), cs_tmp);
+            assert_eq!(val.0, val_tmp);
+        }
+
+        val = super::SpiClock(0x0);
+
+        for i in 0..4 as u8 {
+            let fn_tmp = match i {
+                0x0 => FactorN::N1,
+                0x1 => FactorN::N2,
+                0x2 => FactorN::N4,
+                0x3 => FactorN::N8,
+                _ => unreachable!(),
+            };
+
+            let val_tmp = match i {
+                0x0 => 0x00000000,
+                0x1 => 0x00000100,
+                0x2 => 0x00000200,
+                0x3 => 0x00000300,
+                _ => unreachable!(),
+            };
+
+            val = val.set_factor_n(fn_tmp);
+            assert_eq!(val.factor_n(), fn_tmp);
+            assert_eq!(val.0, val_tmp);
+        }
+
+        val = super::SpiClock(0x0);
+        val = val.set_factor_m(0x03);
+        assert_eq!(val.factor_m(), 0x03);
+        assert_eq!(val.0, 0x00000003);
+    }
+
+    #[test]
+    fn struct_spi_bgr_functions() {
+        let mut val = super::SpiBusGating(0x0);
+
+        val = val.gate_pass::<0>();
+        assert_eq!(val.0, 0x00000001);
+
+        val = val.gate_mask::<0>();
+        assert_eq!(val.0, 0x00000000);
+
+        val = val.deassert_reset::<0>();
+        assert_eq!(val.0, 0x00010000);
+
+        val = val.assert_reset::<0>();
+        assert_eq!(val.0, 0x00000000);
+
+        val = val.gate_pass::<1>();
+        assert_eq!(val.0, 0x00000002);
+
+        val = val.gate_mask::<1>();
+        assert_eq!(val.0, 0x00000000);
+
+        val = val.deassert_reset::<1>();
+        assert_eq!(val.0, 0x00020000);
+
+        val = val.assert_reset::<1>();
+        assert_eq!(val.0, 0x00000000);
+    }
 }

src/smhc.rs

@@ -168,10 +168,21 @@ impl GlobalControl {
     pub const fn set_software_reset(self) -> Self {
         Self(self.0 | Self::SOFT_RST)
     }
-    // Note: DMA_RST, FIFO_RST and SOFT_RST are write-1-set, auto-cleared by hardware.
-    // TODO has_dma_reset.
-    // TODO has_fifo_reset.
-    // TODO has_software_reset.
+    /// Is DMA Reset signal cleared by hardware?
+    #[inline]
+    pub const fn is_dma_reset_cleared(self) -> bool {
+        (self.0 & Self::DMA_RST) == 0
+    }
+    /// Is FIFO Reset signal cleared by hardware?
+    #[inline]
+    pub const fn is_fifo_reset_cleared(self) -> bool {
+        (self.0 & Self::FIFO_RST) == 0
+    }
+    /// Is Software Reset signal cleared by hardware?
+    #[inline]
+    pub const fn is_software_reset_cleared(self) -> bool {
+        (self.0 & Self::SOFT_RST) == 0
+    }
 }
 
 /// Clock control register.
@@ -509,8 +520,11 @@ impl Command {
     pub const fn set_command_index(self, val: u8) -> Self {
         Self((self.0 & !Self::CMD_IDX) | ((val as u32) << 0))
     }
-    // Bit 31 (SMHC_CMD_START, or CMD_LOAD) is write-1-set by software, auto-cleared by hardware.
-    // TODO has_command_start.
+    /// Is command start signal cleared by hardware?
+    #[inline]
+    pub const fn is_command_start_cleared(self) -> bool {
+        (self.0 & Self::CMD_LOAD) == 0
+    }
 }
 
 /// Argument register.
@@ -1057,19 +1071,18 @@ mod tests {
         assert_eq!(val.0, 0x000000000);
 
         val = val.set_dma_reset();
+        assert!(!val.is_dma_reset_cleared());
         assert_eq!(val.0, 0x00000004);
 
         val = GlobalControl(0x0);
         val = val.set_fifo_reset();
+        assert!(!val.is_fifo_reset_cleared());
         assert_eq!(val.0, 0x00000002);
 
         val = GlobalControl(0x0);
         val = val.set_software_reset();
+        assert!(!val.is_software_reset_cleared());
         assert_eq!(val.0, 0x00000001);
-
-        // TODO has_dma_reset
-        // TODO has_fifo_reset
-        // TODO has_software_reset
     }
 
     #[test]
@@ -1146,6 +1159,7 @@ mod tests {
         let mut val = Command(0x0);
 
         val = val.set_command_start();
+        assert!(!val.is_command_start_cleared());
         assert_eq!(val.0, 0x80000000);
 
         val = Command(0x0);
@@ -1232,8 +1246,6 @@ mod tests {
         val = val.set_command_index(0x3F);
         assert_eq!(val.command_index(), 0x3F);
         assert_eq!(val.0, 0x0000003F);
-
-        // TODO has_command_start
     }
 
     #[test]